AT91: Makes AT91SAM9RL SoC build correctly against u-boot-atmel/master

[oweals/u-boot.git] / board / csb272 / init.S

diff --git a/board/csb272/init.S b/board/csb272/init.S
index 15b26f8bf86702fcad3ff9b07f2ca401086092ed..82c6fdb965e235b5c2c995122857148649665356 100644 (file)
--- a/board/csb272/init.S
+++ b/board/csb272/init.S
@@ -22,7 +22,7 @@
  *
  *****************************************************************************/
 #include <config.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 
 #define _LINUX_CONFIG_H 1      /* avoid reading Linux autoconf.h file  */
 
@@ -175,26 +175,26 @@ sdram_init:
         * Disable memory controller to allow
         * values to be changed.
         */
-       WDCR_SDRAM(mem_mcopt1, 0x00000000)
+       WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
 
        /*
         * Configure Memory Banks
         */
-       WDCR_SDRAM(mem_mb0cf, 0x00084001)
-       WDCR_SDRAM(mem_mb1cf, 0x00000000)
-       WDCR_SDRAM(mem_mb2cf, 0x00000000)
-       WDCR_SDRAM(mem_mb3cf, 0x00000000)
+       WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
+       WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
+       WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
+       WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
 
        /*
         * Set up SDTR1 (SDRAM Timing Register)
         */
-       WDCR_SDRAM(mem_sdtr1, 0x00854009)
+       WDCR_SDRAM(SDRAM0_TR, 0x00854009)
 
        /*
         * Set RTR (Refresh Timing Register)
         */
-       WDCR_SDRAM(mem_rtr,   0x10000000)
-       /* WDCR_SDRAM(mem_rtr,   0x05f00000) */
+       WDCR_SDRAM(SDRAM0_RTR,   0x10000000)
+       /* WDCR_SDRAM(SDRAM0_RTR,   0x05f00000) */
 
        /********************************************************************
         * Delay to ensure 200usec have elapsed since reset. Assume worst
@@ -210,7 +210,7 @@ sdram_init:
        /********************************************************************
         * Set memory controller options reg, MCOPT1.
         *******************************************************************/
-       WDCR_SDRAM(mem_mcopt1,0x80800000)
+       WDCR_SDRAM(SDRAM0_CFG,0x80800000)
 
 ..sdri_done:
        blr                             /* Return to calling function */