mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flash

[oweals/u-boot.git] / board / csb272 / csb272.c

diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
index 740e3ac6f5e9b22741cceb2d5dcc87647a4d361e..1ed3e1b6a4e5c6c36b3eeff4c27e28fc0fc58347 100644 (file)
--- a/board/csb272/csb272.c
+++ b/board/csb272/csb272.c
@@ -129,34 +129,34 @@ phys_size_t initdram (int board_type)
        /*
         * ToDo: Move the asm init routine sdram_init() to this C file,
         * or even better use some common ppc4xx code available
-        * in cpu/ppc4xx
+        * in arch/powerpc/cpu/ppc4xx
         */
        sdram_init();
 
        tot_size = 0;
 
-       mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
        tmp = mfdcr (SDRAM0_CFGDATA);
        if (tmp & 0x00000001) {
                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
                tot_size += bank_size;
        }
 
-       mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
        tmp = mfdcr (SDRAM0_CFGDATA);
        if (tmp & 0x00000001) {
                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
                tot_size += bank_size;
        }
 
-       mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
        tmp = mfdcr (SDRAM0_CFGDATA);
        if (tmp & 0x00000001) {
                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
                tot_size += bank_size;
        }
 
-       mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
        tmp = mfdcr (SDRAM0_CFGDATA);
        if (tmp & 0x00000001) {
                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);