fix easylogo on big endian dev systems

[oweals/u-boot.git] / board / cray / L1 / init.S

diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S
index acc52051f9bdf74a76fa2ba5d0fb039a844d11d3..72a10d3a1bf499f5892726b77698167dad062d79 100644 (file)
--- a/board/cray/L1/init.S
+++ b/board/cray/L1/init.S
@@ -52,53 +52,53 @@
 /*     control registers to set that up are determined by what we've */
 /*     empirically discovered work there. */
 
-       .globl  ext_bus_cntlr_init
+       .globl  ext_bus_cntlr_init
 ext_bus_cntlr_init:
-        mflr    r4                      /* save link register */
-        bl      ..getAddr
+       mflr    r4                      /* save link register */
+       bl      ..getAddr
 ..getAddr:
-        mflr    r3                      /* get address of ..getAddr */
-        mtlr    r4                      /* restore link register */
-        addi    r4,0,14                 /* set ctr to 10; used to prefetch */
-        mtctr   r4                      /* 10 cache lines to fit this function */
-                                        /* in cache (gives us 8x10=80 instrctns) */
+       mflr    r3                      /* get address of ..getAddr */
+       mtlr    r4                      /* restore link register */
+       addi    r4,0,14                 /* set ctr to 10; used to prefetch */
+       mtctr   r4                      /* 10 cache lines to fit this function */
+                                       /* in cache (gives us 8x10=80 instrctns) */
 ..ebcloop:
-        icbt    r0,r3                   /* prefetch cache line for addr in r3 */
-        addi    r3,r3,32               /* move to next cache line */
-        bdnz    ..ebcloop               /* continue for 10 cache lines */
+       icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+       addi    r3,r3,32                /* move to next cache line */
+       bdnz    ..ebcloop               /* continue for 10 cache lines */
 
-        /*------------------------------------------------------------------- */
-        /* Delay to ensure all accesses to ROM are complete before changing */
+       /*------------------------------------------------------------------- */
+       /* Delay to ensure all accesses to ROM are complete before changing */
            /* bank 0 timings. 200usec should be enough. */
-        /*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
-        /*------------------------------------------------------------------- */
+       /*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+       /*------------------------------------------------------------------- */
        addis   r3,0,0x0
-        ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
-        mtctr   r3
+       ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+       mtctr   r3
 ..spinlp:
-        bdnz    ..spinlp                /* spin loop */
+       bdnz    ..spinlp                /* spin loop */
 
 
-        /*---------------------------------------------------------------------- */
-        /* Peripheral Bank 0 (Flash) initialization */
-        /*---------------------------------------------------------------------- */
+       /*---------------------------------------------------------------------- */
+       /* Peripheral Bank 0 (Flash) initialization */
+       /*---------------------------------------------------------------------- */
                /* 0x7F8FFE80 slowest boot */
-        addi    r4,0,pb0ap
-        mtdcr   ebccfga,r4
-        addis   r4,0,0x9B01
-        ori     r4,r4,0x5480
-        mtdcr   ebccfgd,r4
-
-        addi    r4,0,pb0cr
-        mtdcr   ebccfga,r4
-        addis   r4,0,0xFFC5           /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
-        ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
-        mtdcr   ebccfgd,r4
-
-        blr
-
-        /*---------------------------------------------------------------------- */
-        /* Peripheral Bank 1 (NVRAM/RTC) initialization */
+       addi    r4,0,pb0ap
+       mtdcr   ebccfga,r4
+       addis   r4,0,0x9B01
+       ori     r4,r4,0x5480
+       mtdcr   ebccfgd,r4
+
+       addi    r4,0,pb0cr
+       mtdcr   ebccfga,r4
+       addis   r4,0,0xFFC5           /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
+       ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
+       mtdcr   ebccfgd,r4
+
+       blr
+
+       /*---------------------------------------------------------------------- */
+       /* Peripheral Bank 1 (NVRAM/RTC) initialization */
                /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
                /* and we do DMA on it.  The ConfigurationRegister part is threfore */
                /* almost arbitrary, except that our linux driver needs to know the */
@@ -119,21 +119,21 @@ ext_bus_cntlr_init:
                /* ByteEnableMode                       BEM=0 */
                /* ParityEnable                         PEN=0 */
                /* all reserved bits=0 */
-        /*---------------------------------------------------------------------- */
-        /*---------------------------------------------------------------------- */
-        addi    r4,0,pb1ap
-        mtdcr   ebccfga,r4
-        addis   r4,0,0x0185            /* hiword */
-        ori     r4,r4,0x4380   /* loword */
-        mtdcr   ebccfgd,r4
-
-        addi    r4,0,pb1cr
-        mtdcr   ebccfga,r4
-        addis   r4,0,0xF001           /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
-        ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
-        mtdcr   ebccfgd,r4
-
-        blr
+       /*---------------------------------------------------------------------- */
+       /*---------------------------------------------------------------------- */
+       addi    r4,0,pb1ap
+       mtdcr   ebccfga,r4
+       addis   r4,0,0x0185             /* hiword */
+       ori     r4,r4,0x4380    /* loword */
+       mtdcr   ebccfgd,r4
+
+       addi    r4,0,pb1cr
+       mtdcr   ebccfga,r4
+       addis   r4,0,0xF001           /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
+       ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
+       mtdcr   ebccfgd,r4
+
+       blr
 
 /*----------------------------------------------------------------------------- */
 /* Function:   sdram_init */
@@ -141,7 +141,7 @@ ext_bus_cntlr_init:
 /*                             NOTE: for CrayL1 we have ECC memory, so enable it. */
 /*....now done in C in L1.c:init_sdram for readability. */
 /*----------------------------------------------------------------------------- */
-        .globl  sdram_init
+       .globl  sdram_init
 
 sdram_init:
  blr