powerpc: ppc4xx: remove board support for KAREF and METROBOX

[oweals/u-boot.git] / board / cray / L1 / L1.c

diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c
index 5d1c4170dd104fff4e1a2a5f3ad052c250faa896..d706ff10d343bcc86a2a08fa74cf4a615e3cda03 100644 (file)
--- a/board/cray/L1/L1.c
+++ b/board/cray/L1/L1.c
@@ -2,28 +2,12 @@
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/processor.h>
-#include <4xx_i2c.h>
+#include <asm/ppc4xx-i2c.h>
 #include <command.h>
 #include <rtc.h>
 #include <post.h>
@@ -113,13 +97,13 @@ int board_early_init_f (void)
 {
        /* Running from ROM: global data is still READONLY */
        init_sdram ();
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000020);      /* set all but FPGA SMI to be non-critical */
-       mtdcr (uicpr, 0xFFFFFFE0);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
+       mtdcr (UIC0CR, 0x00000020);     /* set all but FPGA SMI to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFFE0);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
        return 0;
 }
 
@@ -169,12 +153,6 @@ int misc_init_r (void)
        return (0);
 }
 
-/* ------------------------------------------------------------------------- */
-phys_size_t initdram (int board_type)
-{
-       return (L1_MEMSIZE);
-}
-
 /* ------------------------------------------------------------------------- */
 /* stubs so we can print dates w/o any nvram RTC.*/
 int rtc_get (struct rtc_time *tmp)
@@ -198,7 +176,7 @@ static void init_sdram (void)
  unsigned long tmp;
 
        /* write SDRAM bank 0 register */
-       mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
        mtdcr (SDRAM0_CFGDATA, 0x00062001);
 
 /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.     */
@@ -212,25 +190,25 @@ static void init_sdram (void)
        /* divisor = ((mfdcr(strap)>> 28) & 0x3); */
 
 /* write SDRAM timing for 100MHz. */
-       mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
        mtdcr (SDRAM0_CFGDATA, 0x0086400D);
 
 /* write SDRAM refresh interval register */
-       mtdcr (SDRAM0_CFGADDR, mem_rtr);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
        mtdcr (SDRAM0_CFGDATA, 0x05F00000);
        udelay (200);
 
 /* sdram controller.*/
-       mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
        mtdcr (SDRAM0_CFGDATA, 0x90800000);
        udelay (200);
 
 /* initially, disable ECC on all banks */
        udelay (200);
-       mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
        tmp = mfdcr (SDRAM0_CFGDATA);
        tmp &= 0xff0fffff;
-       mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
        mtdcr (SDRAM0_CFGDATA, tmp);
 
        return;
@@ -245,7 +223,7 @@ int testdram (void)
        uint *pend = (uint *) L1_MEMSIZE;
        uint *p;
 
-       if (getenv_r("booted",NULL,0) <= 0)
+       if (getenv_f("booted",NULL,0) <= 0)
        {
                printf ("testdram..");
        /*AA*/
@@ -282,15 +260,15 @@ int testdram (void)
        }
        printf ("Enable ECC..");
 
-       mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
        tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
-       mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
        mtdcr (SDRAM0_CFGDATA, tmp);
        udelay (600);
        for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
                ;
        udelay (400);
-       mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
        tmp = mfdcr (SDRAM0_CFGDATA);
        tmp |= 0x00800000;
        mtdcr (SDRAM0_CFGDATA, tmp);