#include <i2c.h>
#include <usb.h>
#include <mmc.h>
-#include <nand.h>
#include <twl4030.h>
-#include <bmp_layout.h>
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/ehci-omap.h>
#include <asm/gpio.h>
+#include "../common/common.h"
#include "../common/eeprom.h"
DECLARE_GLOBAL_DATA_PTR;
0
};
-static u32 gpmc_nand_config[GPMC_MAX_REG] = {
- SMNAND_GPMC_CONFIG1,
- SMNAND_GPMC_CONFIG2,
- SMNAND_GPMC_CONFIG3,
- SMNAND_GPMC_CONFIG4,
- SMNAND_GPMC_CONFIG5,
- SMNAND_GPMC_CONFIG6,
- 0,
-};
-
-#ifdef CONFIG_LCD
-#ifdef CONFIG_CMD_NAND
-static int splash_load_from_nand(u32 bmp_load_addr)
-{
- struct bmp_header *bmp_hdr;
- int res, splash_screen_nand_offset = 0x100000;
- size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
-
- if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
- goto splash_address_too_high;
-
- res = nand_read_skip_bad(&nand_info[nand_curr_device],
- splash_screen_nand_offset, &bmp_header_size,
- NULL, nand_info[nand_curr_device].size,
- (u_char *)bmp_load_addr);
- if (res < 0)
- return res;
-
- bmp_hdr = (struct bmp_header *)bmp_load_addr;
- bmp_size = le32_to_cpu(bmp_hdr->file_size);
-
- if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
- goto splash_address_too_high;
-
- return nand_read_skip_bad(&nand_info[nand_curr_device],
- splash_screen_nand_offset, &bmp_size,
- NULL, nand_info[nand_curr_device].size,
- (u_char *)bmp_load_addr);
-
-splash_address_too_high:
- printf("Error: splashimage address too high. Data overwrites U-Boot "
- "and/or placed beyond DRAM boundaries.\n");
-
- return -1;
-}
-#else
-static inline int splash_load_from_nand(void)
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
{
- return -1;
+ timings->mr = MICRON_V_MR_165;
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
-#endif /* CONFIG_CMD_NAND */
+#endif
+
+#define CM_T35_SPLASH_NAND_OFFSET 0x100000
int splash_screen_prepare(void)
{
- char *env_splashimage_value;
- u32 bmp_load_addr;
-
- env_splashimage_value = getenv("splashimage");
- if (env_splashimage_value == NULL)
- return -1;
-
- bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
- if (bmp_load_addr == 0) {
- printf("Error: bad splashimage address specified\n");
- return -1;
- }
-
- return splash_load_from_nand(bmp_load_addr);
+ return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET);
}
-#endif /* CONFIG_LCD */
/*
* Routine: board_init
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
- CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
-
/* board id for Linux */
if (get_cpu_family() == CPU_OMAP34XX)
gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
return 0;
}
-static u32 cm_t3x_rev;
-
/*
* Routine: get_board_rev
* Description: read system revision
*/
u32 get_board_rev(void)
{
- if (!cm_t3x_rev)
- cm_t3x_rev = cl_eeprom_get_board_rev();
-
- return cm_t3x_rev;
+ return cl_eeprom_get_board_rev();
};
-/*
- * Routine: misc_init_r
- * Description: display die ID
- */
int misc_init_r(void)
{
- u32 board_rev = get_board_rev();
- u32 rev_major = board_rev / 100;
- u32 rev_minor = board_rev - (rev_major * 100);
-
- if ((rev_minor / 10) * 10 == rev_minor)
- rev_minor = rev_minor / 10;
-
- printf("PCB: %u.%u\n", rev_major, rev_minor);
+ cl_print_pcb_info();
dieid_num_r();
return 0;
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
cm_t3730_set_muxconf();
}
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#define SB_T35_WP_GPIO 59
+
int board_mmc_getcd(struct mmc *mmc)
{
u8 val;
int board_mmc_init(bd_t *bis)
{
- return omap_mmc_init(0, 0, 0, -1, 59);
+ return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO);
}
#endif
#define SB_T35_USB_HUB_RESET_GPIO 167
int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
u8 val;
int offset;
- if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) {
- printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset",
- SB_T35_USB_HUB_RESET_GPIO);
- return -1;
- }
-
- gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0);
- udelay(10);
- gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
- udelay(1000);
+ cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
int ehci_hcd_stop(void)
{
+ cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
return omap_ehci_hcd_stop();
}
#endif /* CONFIG_USB_EHCI_OMAP */
projects / oweals / u-boot.git / blobdiff