arm: at91: pmc: replace the constant with a define in at91_pmc.h

[oweals/u-boot.git] / board / atmel / sama5d4_xplained / sama5d4_xplained.c

diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index de0baada287689529f70469182b6c37603974c92..db4533148049a6ffce22cff1a92e82dc5cab3d19 100644 (file)
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -10,11 +10,13 @@
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/sama5d3_smc.h>
 #include <asm/arch/sama5d4.h>
-#include <atmel_lcdc.h>
+#include <atmel_hlcdc.h>
 #include <atmel_mci.h>
 #include <lcd.h>
 #include <mmc.h>
@@ -22,6 +24,7 @@
 #include <netdev.h>
 #include <nand.h>
 #include <spi.h>
+#include <version.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -109,10 +112,8 @@ static void sama5d4_xplained_usb_hw_init(void)
 vidinfo_t panel_info = {
        .vl_col = 480,
        .vl_row = 272,
-       .vl_clk = 9000,
-       .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL,
+       .vl_clk = 9000000,
        .vl_bpix = LCD_BPP,
-       .vl_bpox = LCD_OUTPUT_BPP,
        .vl_tft = 1,
        .vl_hsync_len = 41,
        .vl_left_margin = 2,
@@ -179,6 +180,7 @@ void lcd_show_board_info(void)
        int i;
        char temp[32];
 
+       lcd_printf("%s\n", U_BOOT_VERSION);
        lcd_printf("2014 ATMEL Corp\n");
        lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
                   strmhz(temp, get_cpu_clk_rate()));
@@ -228,6 +230,9 @@ void sama5d4_xplained_mci1_hw_init(void)
 
 int board_mmc_init(bd_t *bis)
 {
+       /* Enable the power supply */
+       at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
+
        return atmel_mci_init((void *)ATMEL_BASE_MCI1);
 }
 #endif /* CONFIG_GENERIC_ATMEL_MCI */
@@ -296,6 +301,9 @@ int board_init(void)
 #ifdef CONFIG_CMD_USB
        sama5d4_xplained_usb_hw_init();
 #endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+       at91_udp_hw_init();
+#endif
 
        return 0;
 }
@@ -315,5 +323,96 @@ int board_eth_init(bd_t *bis)
        rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
 #endif
 
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+       usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+       usb_eth_initialize(bis);
+#endif
+#endif
+
        return rc;
 }
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+       sama5d4_xplained_mci1_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+       sama5d4_xplained_nand_hw_init();
+#elif CONFIG_SYS_USE_SERIALFLASH
+       sama5d4_xplained_spi0_hw_init();
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+       ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+       ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+                   ATMEL_MPDDRC_CR_NR_ROW_14 |
+                   ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+                   ATMEL_MPDDRC_CR_NB_8BANKS |
+                   ATMEL_MPDDRC_CR_NDQS_DISABLED |
+                   ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+                   ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+       ddr2->rtr = 0x2b0;
+
+       ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+                     3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+                     3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+                     10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+                     3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+       ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+                     200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+                     25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+                     23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+       ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+                     3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+                     8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       struct atmel_mpddr ddr2;
+
+       ddr2_conf(&ddr2);
+
+       /* enable MPDDR clock */
+       at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+       writel(AT91_PMC_DDR, &pmc->scer);
+
+       /* DDRAM2 Controller initialize */
+       ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       u32 tmp;
+
+       tmp = AT91_PMC_PLLAR_29 |
+             AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+             AT91_PMC_PLLXR_MUL(87) |
+             AT91_PMC_PLLXR_DIV(1);
+       at91_plla_init(tmp);
+
+       writel(0x0 << 8, &pmc->pllicpr);
+
+       tmp = AT91_PMC_MCKR_H32MXDIV |
+             AT91_PMC_MCKR_PLLADIV_2 |
+             AT91_PMC_MCKR_MDIV_3 |
+             AT91_PMC_MCKR_CSS_PLLA;
+       at91_mck_init(tmp);
+}
+#endif