reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
- mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
- mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
-
- mtebc(pb1ap, 0x00000000);
- mtebc(pb1cr, 0x00000000);
-
- mtebc(pb2ap, 0x04814500);
- /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
-
- mtebc(pb3ap, 0x00000000);
- mtebc(pb3cr, 0x00000000);
-
- mtebc(pb4ap, 0x00000000);
- mtebc(pb4cr, 0x00000000);
-
- mtebc(pb5ap, 0x00000000);
- mtebc(pb5cr, 0x00000000);
-
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
/* external interrupts IRQ0...3 */
- out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
- out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
+ out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
+ out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
+#ifdef CONFIG_440EP
/*setup USB 2.0 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
+#endif
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
/*enable ethernet */
*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
+#ifdef CONFIG_440EP
/*enable usb 1.1 fs device and remove usb 2.0 reset */
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
+#endif
/*get rid of flash write protect */
*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
int checkboard(void)
{
char *s = getenv("serial#");
+ u8 rev;
+ u8 val;
+#ifdef CONFIG_440EP
printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
+#else
+ printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
+#endif
+
+ rev = *(u8 *)(CFG_CPLD + 0);
+ val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+ printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
+
if (s != NULL) {
puts(", serial# ");
puts(s);
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
- mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
+ mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
- mtsdram(mem_cfg0, 0x84000000); /* Enable */
+ mtsdram(mem_cfg0, 0x80000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);
* certain pre-initialization actions.
*
************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
return 1;
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
}
#endif
+
+void board_reset(void)
+{
+ /* give reset to BCSR */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09;
+}