Merge branch 'master' of git://git.denx.de/u-boot-video

[oweals/u-boot.git] / board / amcc / kilauea / kilauea.c

diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index 1caa2fd43518924bb466d2bf5a708e438a62c9e5..7e84a61a96da1a3e7d00f3c7de73bc96c8cee3df 100644 (file)
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -36,7 +36,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips   */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips    */
 
 /*
  * Board early initialization function
@@ -197,7 +197,7 @@ int board_early_init_f (void)
                SDR0_CUST0_NDFC_ENABLE |
                SDR0_CUST0_NDFC_BW_8_BIT |
                SDR0_CUST0_NRB_BUSY |
-               (0x80000000 >> (28 + CFG_NAND_CS));
+               (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
        mtsdr(SDR0_CUST0, val);
 
        /*
@@ -210,9 +210,9 @@ int board_early_init_f (void)
        /*
         * Configure FPGA register with PCIe reset
         */
-       out_be32((void *)CFG_FPGA_BASE, 0xff570cc4);    /* assert PCIe reset */
+       out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4);     /* assert PCIe reset */
        mdelay(50);
-       out_be32((void *)CFG_FPGA_BASE, 0xff570cc7);    /* deassert PCIe reset */
+       out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7);     /* deassert PCIe reset */
 
        return 0;
 }
@@ -222,7 +222,7 @@ int misc_init_r(void)
 #ifdef CONFIG_ENV_IS_IN_FLASH
        /* Monitor protection ON by default */
        flash_protect(FLAG_PROTECT_SET,
-                     -CFG_MONITOR_LEN,
+                     -CONFIG_SYS_MONITOR_LEN,
                      0xffffffff,
                      &flash_info[0]);
 #endif
@@ -330,9 +330,9 @@ void pcie_setup_hoses(int busno)
 
                /* setup mem resource */
                pci_set_region(hose->regions + 0,
-                              CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-                              CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-                              CFG_PCIE_MEMSIZE,
+                              CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+                              CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+                              CONFIG_SYS_PCIE_MEMSIZE,
                               PCI_REGION_MEM);
                hose->region_count = 1;
                pci_register_hose(hose);
@@ -374,34 +374,3 @@ int post_hotkeys_pressed(void)
        return 0;       /* No hotkeys supported */
 }
 #endif /* CONFIG_POST */
-
-#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
-/*
- * This is for quicker auto calibration boot up once WRDTR and CLKTR
- * values for the kilauea board were determined and are therefore known.
- *
- * Use these scan options for PLB bus greater than or equal 200MHz
- * else use the defaults. These options are known to return a cycle
- * delay of T2 or better with a 200MHz PLB bus. Scanning the
- * full list of WDTR/CLKTR should work, but currently it does not.
- * HW team is investigating.
- */
-/* List of (SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CLKP]) pairs to try */
-struct sdram_timing quick_scan_options[] = {
-       {0, 3}, {1, 1}, {1, 2}, {1, 3},
-       {2, 1}, {2, 2}, {2, 3}, {3, 1},
-       {3, 2}, {4, 1}, {-1, -1}
-};
-
-ulong ddr_scan_option(ulong default_val)
-{
-       PPC4xx_SYS_INFO board_cfg;
-
-       get_sys_info(&board_cfg);
-
-       if (board_cfg.freqPLB >= 200000000)
-               return (ulong)(quick_scan_options);
-       else
-               return (ulong)default_val;
-}
-#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */