Merge branch 'master' of git://www.denx.de/git/u-boot-coldfire

[oweals/u-boot.git] / board / amcc / kilauea / kilauea.c

diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index 96c0dd460039b3acefc6d5deed0c36ff6d81e7b8..37ef06ef2a77648fd26c482ff2873afd9819a7f7 100644 (file)
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -25,6 +25,7 @@
 #include <ppc4xx.h>
 #include <ppc405.h>
 #include <libfdt.h>
+#include <fdt_support.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 
@@ -191,13 +192,6 @@ int board_early_init_f (void)
         */
        mtsdr(SDR0_SRST, 0);
 
-       /*
-        * Configure FPGA register with PCIe reset
-        */
-       out_be32((void *)CFG_FPGA_BASE, 0xff570cc0);    /* assert PCIe reset */
-       mdelay(50);
-       out_be32((void *)CFG_FPGA_BASE, 0xff570cc3);    /* deassert PCIe reset */
-
        /* Configure 405EX for NAND usage */
        val = SDR0_CUST0_MUX_NDFC_SEL |
                SDR0_CUST0_NDFC_ENABLE |
@@ -213,6 +207,13 @@ int board_early_init_f (void)
        val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
        mtsdr(SDR0_PFC1, val);
 
+       /*
+        * Configure FPGA register with PCIe reset
+        */
+       out_be32((void *)CFG_FPGA_BASE, 0xff570cc4);    /* assert PCIe reset */
+       mdelay(50);
+       out_be32((void *)CFG_FPGA_BASE, 0xff570cc7);    /* deassert PCIe reset */
+
        return 0;
 }