Merge branch 'master' of git://git.denx.de/u-boot-arm

[oweals/u-boot.git] / board / amcc / bamboo / bamboo.c

diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 2ffd720d5c4f80d29b56f6e0ceed816435c6ac96..2598f2cf41d703abeb210c487144bc098b9e9b3a 100644 (file)
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -392,21 +392,21 @@ int board_early_init_f(void)
        /*--------------------------------------------------------------------
         * Setup the interrupt controller polarities, triggers, etc.
         *-------------------------------------------------------------------*/
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000009);      /* ATI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 
        /*--------------------------------------------------------------------
         * Setup the GPIO pins
@@ -542,22 +542,22 @@ void pci_target_init(struct pci_controller *hose)
          |   Use byte reversed out routines to handle endianess.
          | Make this region non-prefetchable.
          +--------------------------------------------------------------------------*/
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
 
        /*--------------------------------------------------------------------------+
         * Set up Configuration registers