Code cleanup. Update CHANGELOG

[oweals/u-boot.git] / board / amcc / acadia / memory.c

diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 0f1de71c1ba3f21e5cc1522bba99bec24ccfe9be..a1b015519a7f12be718f895aa5c894c0ba862eea 100644 (file)
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -55,7 +55,6 @@ void sdram_init(void)
        if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) {
                mtspr(SPRG7, LOAK_NONE);        /* "NONE" */
        }
-
 #if 1
        /*
         * When running the NAND SPL, the normal EBC configuration is not
@@ -77,7 +76,6 @@ void sdram_init(void)
        mtspr(SPRG6, LOAK_SPL); /* "SPL " */
        mtspr(SPRG7, LOAK_OCM); /* "OCM " */
 #endif
-
        return;
 }
 
@@ -98,14 +96,12 @@ static void cram_bcr_write(u32 wr_val)
        wr_val = wr_val << 2;
        /* wr_val = 0x1c048; */
 
-
        /*
         * # stop PLL clock before programming CRAM
         * set EPLD0_MUX_CTL.OESPR3 = 1
         * delay 2
         */
 
-
        /*
         * # CS1
         * read 0x00200000
@@ -147,7 +143,6 @@ static void cram_bcr_write(u32 wr_val)
         * set EPLD0_MUX_CTL.OESPR3 = 0
         */
 
-
        /*
         * set CRAMCR = 0x1
         */
@@ -254,9 +249,6 @@ static u32 is_cram(void)
                gpio_reg = in32(GPIO1_OR);
                out32(GPIO1_OR,  gpio_reg | 0x00000400);
 
-
-
-
                /* Read Version ID */
                cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR);
                udelay(100000);
@@ -309,8 +301,7 @@ static long int cram_init(u32 already_inited)
         * In the case of NAND boot and SPI boot, CRAM will already be
         * initialized by the pre-loader
         */
-       if (already_inited != 1)
-       {
+       if (already_inited != 1) {
                /*
                 * #o CRAM Card
                 * #  - CRAMCRE @reg16 = 1; for CRAM to use
@@ -323,7 +314,6 @@ static long int cram_init(u32 already_inited)
                 * #end
                 */
 
-
                /*
                 * #1. EBC need to program READY, CLK, ADV for ASync mode
                 * # config output
@@ -448,8 +438,6 @@ static long int cram_init(u32 already_inited)
                /*
                 * set EPLD0_MUX_CTL.OESPR3 = 0
                 */
-
-
                mtspr(SPRG7, LOAK_CRAM);        /* "CRAM" */
        } /* if (already_inited != 1) */