imx8: Configure SNVS

[oweals/u-boot.git] / board / Marvell / db-88f6820-gp / db-88f6820-gp.c

diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index e700781103fbdf4cf231a062fb8c5eac3adb99b8..1a0746b9d3d5b00e4e6b6a929edfb79d9cca4120 100644 (file)
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -12,15 +11,11 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 
-#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
 #include <../serdes/a38x/high_speed_env_spec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define ETH_PHY_CTRL_REG               0
-#define ETH_PHY_CTRL_POWER_DOWN_BIT    11
-#define ETH_PHY_CTRL_POWER_DOWN_MASK   (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
-
 /*
  * Those values and defines are taken from the Marvell U-Boot version
  * "u-boot-2013.01-2014_T3.0"
@@ -77,7 +72,8 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  * be used by the DDR3 init code in the SPL U-Boot version to configure
  * the DDR3 controller.
  */
-static struct hws_topology_map board_topology_map = {
+static struct mv_ddr_topology_map board_topology_map = {
+       DEBUG_LEVEL_ERROR,
        0x1, /* active interfaces */
        /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
        { { { {0x1, 0, 0, 0},
@@ -86,16 +82,19 @@ static struct hws_topology_map board_topology_map = {
              {0x1, 0, 0, 0},
              {0x1, 0, 0, 0} },
            SPEED_BIN_DDR_1866L,        /* speed_bin */
-           BUS_WIDTH_8,                /* memory_width */
-           MEM_4G,                     /* mem_size */
-           DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
-           HWS_TEMP_LOW} },            /* temperature */
-       5,                              /* Num Of Bus Per Interface*/
-       BUS_MASK_32BIT                  /* Busses mask */
+           MV_DDR_DEV_WIDTH_8BIT,      /* memory_width */
+           MV_DDR_DIE_CAP_4GBIT,       /* mem_size */
+           MV_DDR_FREQ_800,            /* frequency */
+           0, 0,                       /* cas_wl cas_l */
+           MV_DDR_TEMP_LOW,            /* temperature */
+           MV_DDR_TIM_DEFAULT} },      /* timing */
+       BUS_MASK_32BIT,                 /* Busses mask */
+       MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
+       { {0} },                        /* raw spd data */
+       {0}                             /* timing parameters */
 };
 
-struct hws_topology_map *ddr3_get_topology_map(void)
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
 {
        /* Return the board topology as defined in the board code */
        return &board_topology_map;