env: Move env_set() to env.h

[oweals/u-boot.git] / board / LaCie / common / common.c

diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c
index dc5350dc281219babe1b0c16fcda4181645379f1..52880a16fad3c4add82420278b467dc135bf4c98 100644 (file)
--- a/board/LaCie/common/common.c
+++ b/board/LaCie/common/common.c
@@ -1,10 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
  */
 
 #include <common.h>
@@ -13,41 +9,62 @@
 
 #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
 
+#define MII_MARVELL_PHY_PAGE           22
+
 #define MV88E1116_LED_FCTRL_REG                10
 #define MV88E1116_CPRSP_CR3_REG                21
 #define MV88E1116_MAC_CTRL_REG         21
-#define MV88E1116_PGADR_REG            22
 #define MV88E1116_RGMII_TXTM_CTRL      (1 << 4)
 #define MV88E1116_RGMII_RXTM_CTRL      (1 << 5)
 
-void mv_phy_88e1116_init(const char *name)
+void mv_phy_88e1116_init(const char *name, u16 phyaddr)
 {
        u16 reg;
-       u16 devadr;
 
        if (miiphy_set_current_dev(name))
                return;
 
-       /* command to read PHY dev address */
-       if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
-               printf("Err..(%s) could not read PHY dev address\n", __func__);
-               return;
-       }
-
        /*
         * Enable RGMII delay on Tx and Rx for CPU port
         * Ref: sec 4.7.2 of chip datasheet
         */
-       miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
-       miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+       miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
+       miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
        reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
-       miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
-       miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+       miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+       miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
+
+       if (miiphy_reset(name, phyaddr) == 0)
+               printf("88E1116 Initialized on %s\n", name);
+}
 
-       /* reset the phy */
-       miiphy_reset(name, devadr);
+void mv_phy_88e1318_init(const char *name, u16 phyaddr)
+{
+       u16 reg;
+
+       if (miiphy_set_current_dev(name))
+               return;
+
+       /*
+        * Set control mode 4 for LED[0].
+        */
+       miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
+       miiphy_read(name, phyaddr, 16, &reg);
+       reg |= 0xf;
+       miiphy_write(name, phyaddr, 16, reg);
+
+       /*
+        * Enable RGMII delay on Tx and Rx for CPU port
+        * Ref: sec 4.7.2 of chip datasheet
+        */
+       miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
+       miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
+       reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
+       miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+       miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
 
-       printf("88E1116 Initialized on %s\n", name);
+       if (miiphy_reset(name, phyaddr) == 0)
+               printf("88E1318 Initialized on %s\n", name);
 }
 #endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */