ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02

[oweals/u-boot.git] / board / CZ.NIC / turris_omnia / turris_omnia.c

diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 86926f805036e7f630c8d6d8f7d65020c9c4f9bb..1f7650cb3610a2b1186bf1f4a1348d6bdba5fc10 100644 (file)
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -1,14 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
  * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
  *
  * Derived from the code for
  *   Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <environment.h>
 #include <i2c.h>
 #include <miiphy.h>
 #include <netdev.h>
@@ -27,7 +27,7 @@
 # include <wdt.h>
 #endif
 
-#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
 #include <../serdes/a38x/high_speed_env_spec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -90,7 +90,7 @@ static struct serdes_map board_serdes_map_sata[] = {
 static bool omnia_detect_sata(void)
 {
        struct udevice *bus, *dev;
-       int ret;
+       int ret, retry = 3;
        u16 mode;
 
        puts("SERDES0 card detect: ");
@@ -106,8 +106,13 @@ static bool omnia_detect_sata(void)
                return false;
        }
 
-       ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2);
-       if (ret) {
+       for (; retry > 0; --retry) {
+               ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2);
+               if (!ret)
+                       break;
+       }
+
+       if (!retry) {
                puts("I2C read failed! Default PEX\n");
                return false;
        }
@@ -195,7 +200,8 @@ static bool omnia_read_eeprom(struct omnia_eeprom *oep)
  * be used by the DDR3 init code in the SPL U-Boot version to configure
  * the DDR3 controller.
  */
-static struct hws_topology_map board_topology_map_1g = {
+static struct mv_ddr_topology_map board_topology_map_1g = {
+       DEBUG_LEVEL_ERROR,
        0x1, /* active interfaces */
        /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
        { { { {0x1, 0, 0, 0},
@@ -204,17 +210,20 @@ static struct hws_topology_map board_topology_map_1g = {
              {0x1, 0, 0, 0},
              {0x1, 0, 0, 0} },
            SPEED_BIN_DDR_1600K,        /* speed_bin */
-           BUS_WIDTH_16,               /* memory_width */
-           MEM_4G,                     /* mem_size */
-           DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
-           HWS_TEMP_NORMAL,            /* temperature */
-           HWS_TIM_2T} },              /* timing (force 2t) */
-       5,                              /* Num Of Bus Per Interface*/
-       BUS_MASK_32BIT                  /* Busses mask */
+           MV_DDR_DEV_WIDTH_16BIT,     /* memory_width */
+           MV_DDR_DIE_CAP_4GBIT,                       /* mem_size */
+           MV_DDR_FREQ_800,            /* frequency */
+           0, 0,                       /* cas_wl cas_l */
+           MV_DDR_TEMP_NORMAL,         /* temperature */
+           MV_DDR_TIM_2T} },           /* timing */
+       BUS_MASK_32BIT,                 /* Busses mask */
+       MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
+       { {0} },                        /* raw spd data */
+       {0}                             /* timing parameters */
 };
 
-static struct hws_topology_map board_topology_map_2g = {
+static struct mv_ddr_topology_map board_topology_map_2g = {
+       DEBUG_LEVEL_ERROR,
        0x1, /* active interfaces */
        /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
        { { { {0x1, 0, 0, 0},
@@ -223,17 +232,19 @@ static struct hws_topology_map board_topology_map_2g = {
              {0x1, 0, 0, 0},
              {0x1, 0, 0, 0} },
            SPEED_BIN_DDR_1600K,        /* speed_bin */
-           BUS_WIDTH_16,               /* memory_width */
-           MEM_8G,                     /* mem_size */
-           DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
-           HWS_TEMP_NORMAL,            /* temperature */
-           HWS_TIM_2T} },              /* timing (force 2t) */
-       5,                              /* Num Of Bus Per Interface*/
-       BUS_MASK_32BIT                  /* Busses mask */
+           MV_DDR_DEV_WIDTH_16BIT,     /* memory_width */
+           MV_DDR_DIE_CAP_8GBIT,                       /* mem_size */
+           MV_DDR_FREQ_800,            /* frequency */
+           0, 0,                       /* cas_wl cas_l */
+           MV_DDR_TEMP_NORMAL,         /* temperature */
+           MV_DDR_TIM_2T} },           /* timing */
+       BUS_MASK_32BIT,                 /* Busses mask */
+       MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
+       { {0} },                        /* raw spd data */
+       {0}                             /* timing parameters */
 };
 
-struct hws_topology_map *ddr3_get_topology_map(void)
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
 {
        static int mem = 0;
        struct omnia_eeprom oep;
@@ -280,7 +291,7 @@ static int set_regdomain(void)
                puts("EEPROM regdomain read failed.\n");
 
        printf("Regdomain set to %s\n", rd);
-       return setenv("regdomain", rd);
+       return env_set("regdomain", rd);
 }
 #endif
 
@@ -310,7 +321,11 @@ int board_early_init_f(void)
        writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
        writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
 
-       /* Disable I2C debug mode blocking 0x64 I2C address */
+       /*
+        * Disable I2C debug mode blocking 0x64 I2C address.
+        * Note: that would be redundant once Turris Omnia migrates to DM_I2C,
+        * because the mvtwsi driver includes equivalent code.
+        */
        i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
        i2c_debug_reg &= ~(1<<18);
        writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
@@ -510,17 +525,17 @@ int misc_init_r(void)
        mac[5] = mac1[3];
 
        if (is_valid_ethaddr(mac))
-               eth_setenv_enetaddr("ethaddr", mac);
+               eth_env_set_enetaddr("ethaddr", mac);
 
        increment_mac(mac);
 
        if (is_valid_ethaddr(mac))
-               eth_setenv_enetaddr("eth1addr", mac);
+               eth_env_set_enetaddr("eth1addr", mac);
 
        increment_mac(mac);
 
        if (is_valid_ethaddr(mac))
-               eth_setenv_enetaddr("eth2addr", mac);
+               eth_env_set_enetaddr("eth2addr", mac);
 
 out:
 #endif