tools: imx8m_image: Change source path for DDR firmware to build dir

[oweals/u-boot.git] / board / AndesTech / ax25-ae350 / ax25-ae350.c

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
index d343453f22d01a211a03f74d1f47a925881e1fd8..47e692936503da50304343302d902dc16baf7636 100644 (file)
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -11,6 +11,8 @@
 #include <linux/io.h>
 #include <faraday/ftsmc020.h>
 #include <fdtdec.h>
+#include <dm.h>
+#include <spl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -28,29 +30,12 @@ int board_init(void)
 
 int dram_init(void)
 {
-       unsigned long sdram_base = PHYS_SDRAM_0;
-       unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
-       unsigned long actual_size;
-
-       actual_size = get_ram_size((void *)sdram_base, expected_size);
-       gd->ram_size = actual_size;
-
-       if (expected_size != actual_size) {
-               printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
-                       actual_size >> 20, expected_size >> 20);
-       }
-
-       return 0;
+       return fdtdec_setup_mem_size_base();
 }
 
 int dram_init_banksize(void)
 {
-       gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
-       gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
-       gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
-
-       return 0;
+       return fdtdec_setup_memory_banksize();
 }
 
 #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
@@ -67,10 +52,6 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
 
 void *board_fdt_blob_setup(void)
 {
-       void **ptr = (void *)&prior_stage_fdt_address;
-       if (fdt_magic(*ptr) == FDT_MAGIC)
-                       return (void *)*ptr;
-
        return (void *)CONFIG_SYS_FDT_BASE;
 }
 
@@ -97,11 +78,45 @@ int smc_init(void)
        return 0;
 }
 
+static void v5l2_init(void)
+{
+       struct udevice *dev;
+
+       uclass_get_device(UCLASS_CACHE, 0, &dev);
+}
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
        smc_init();
+       v5l2_init();
 
        return 0;
 }
 #endif
+
+#ifdef CONFIG_SPL
+void board_boot_order(u32 *spl_boot_list)
+{
+       u8 i;
+       u32 boot_devices[] = {
+#ifdef CONFIG_SPL_RAM_SUPPORT
+               BOOT_DEVICE_RAM,
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+               BOOT_DEVICE_MMC1,
+#endif
+       };
+
+       for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
+               spl_boot_list[i] = boot_devices[i];
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+       /* boot using first FIT config */
+       return 0;
+}
+#endif