Merge branch '2020-05-18-reduce-size-of-common.h'

[oweals/u-boot.git] / arch / x86 / lib / fsp / fsp_common.c

diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index 001494d97dce65e241b2f6266b1c0ffe736e9ab0..cf32b3e512f238ef30fbadafe5fb2ab18c7bcdfb 100644 (file)
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -1,35 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
 #include <errno.h>
+#include <init.h>
+#include <log.h>
+#include <rtc.h>
+#include <acpi/acpi_s3.h>
+#include <asm/cmos_layout.h>
+#include <asm/early_cmos.h>
 #include <asm/io.h>
+#include <asm/mrccache.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/fsp/fsp_support.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkcpu(void)
+{
+       return 0;
+}
+
 int print_cpuinfo(void)
 {
        post_code(POST_CPU_INFO);
        return default_print_cpuinfo();
 }
 
-int board_pci_post_scan(struct pci_controller *hose)
+int fsp_init_phase_pci(void)
 {
        u32 status;
 
        /* call into FspNotify */
        debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
        status = fsp_notify(NULL, INIT_PHASE_PCI);
-       if (status != FSP_SUCCESS)
+       if (status)
                debug("fail, error code %x\n", status);
        else
                debug("OK\n");
 
-       return 0;
+       return status ? -EPERM : 0;
 }
 
 void board_final_cleanup(void)
@@ -39,10 +54,34 @@ void board_final_cleanup(void)
        /* call into FspNotify */
        debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
        status = fsp_notify(NULL, INIT_PHASE_BOOT);
-       if (status != FSP_SUCCESS)
+       if (status)
                debug("fail, error code %x\n", status);
        else
                debug("OK\n");
+}
 
-       return;
+#ifdef CONFIG_HAVE_ACPI_RESUME
+int fsp_save_s3_stack(void)
+{
+       struct udevice *dev;
+       int ret;
+
+       if (gd->arch.prev_sleep_state == ACPI_S3)
+               return 0;
+
+       ret = uclass_get_device(UCLASS_RTC, 0, &dev);
+       if (ret) {
+               debug("Cannot find RTC: err=%d\n", ret);
+               return -ENODEV;
+       }
+
+       /* Save the stack address to CMOS */
+       ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp);
+       if (ret) {
+               debug("Save stack address to CMOS: err=%d\n", ret);
+               return -EIO;
+       }
+
+       return 0;
 }
+#endif