x86: ivybridge: Implement SDRAM init

[oweals/u-boot.git] / arch / x86 / include / asm / arch-ivybridge / pch.h

diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index ae338e3d92aa0bf3985e03130d30a86f82cff456..c6efdb85659ab66c70d0301c09bf3326ca7decf1 100644 (file)
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -31,6 +31,13 @@
 /* PCI Configuration Space (D31:F0): LPC */
 #define PCH_LPC_DEV            PCI_BDF(0, 0x1f, 0)
 
+#define GEN_PMCON_1            0xa0
+#define GEN_PMCON_2            0xa2
+#define GEN_PMCON_3            0xa4
+#define ETR3                   0xac
+#define  ETR3_CWORWRE          (1 << 18)
+#define  ETR3_CF9GR            (1 << 20)
+
 #define PMBASE                 0x40
 #define ACPI_CNTL              0x44
 #define BIOS_CNTL              0xDC
@@ -126,12 +133,97 @@
 #define RPC            0x0400  /* 32bit */
 #define RPFN           0x0404  /* 32bit */
 
+#define TRSR           0x1e00  /*  8bit */
+#define TRCR           0x1e10  /* 64bit */
+#define TWDR           0x1e18  /* 64bit */
+
+#define IOTR0          0x1e80  /* 64bit */
+#define IOTR1          0x1e88  /* 64bit */
+#define IOTR2          0x1e90  /* 64bit */
+#define IOTR3          0x1e98  /* 64bit */
+
+#define TCTL           0x3000  /*  8bit */
+
+#define NOINT          0
+#define INTA           1
+#define INTB           2
+#define INTC           3
+#define INTD           4
+
+#define DIR_IDR                12      /* Interrupt D Pin Offset */
+#define DIR_ICR                8       /* Interrupt C Pin Offset */
+#define DIR_IBR                4       /* Interrupt B Pin Offset */
+#define DIR_IAR                0       /* Interrupt A Pin Offset */
+
+#define PIRQA          0
+#define PIRQB          1
+#define PIRQC          2
+#define PIRQD          3
+#define PIRQE          4
+#define PIRQF          5
+#define PIRQG          6
+#define PIRQH          7
+
+/* IO Buffer Programming */
+#define IOBPIRI                0x2330
+#define IOBPD          0x2334
+#define IOBPS          0x2338
+#define  IOBPS_RW_BX    ((1 << 9)|(1 << 10))
+#define  IOBPS_WRITE_AX        ((1 << 9)|(1 << 10))
+#define  IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
+
+#define D31IP          0x3100  /* 32bit */
+#define D31IP_TTIP     24      /* Thermal Throttle Pin */
+#define D31IP_SIP2     20      /* SATA Pin 2 */
+#define D31IP_SMIP     12      /* SMBUS Pin */
+#define D31IP_SIP      8       /* SATA Pin */
+#define D30IP          0x3104  /* 32bit */
+#define D30IP_PIP      0       /* PCI Bridge Pin */
+#define D29IP          0x3108  /* 32bit */
+#define D29IP_E1P      0       /* EHCI #1 Pin */
+#define D28IP          0x310c  /* 32bit */
+#define D28IP_P8IP     28      /* PCI Express Port 8 */
+#define D28IP_P7IP     24      /* PCI Express Port 7 */
+#define D28IP_P6IP     20      /* PCI Express Port 6 */
+#define D28IP_P5IP     16      /* PCI Express Port 5 */
+#define D28IP_P4IP     12      /* PCI Express Port 4 */
+#define D28IP_P3IP     8       /* PCI Express Port 3 */
+#define D28IP_P2IP     4       /* PCI Express Port 2 */
+#define D28IP_P1IP     0       /* PCI Express Port 1 */
+#define D27IP          0x3110  /* 32bit */
+#define D27IP_ZIP      0       /* HD Audio Pin */
+#define D26IP          0x3114  /* 32bit */
+#define D26IP_E2P      0       /* EHCI #2 Pin */
+#define D25IP          0x3118  /* 32bit */
+#define D25IP_LIP      0       /* GbE LAN Pin */
+#define D22IP          0x3124  /* 32bit */
+#define D22IP_KTIP     12      /* KT Pin */
+#define D22IP_IDERIP   8       /* IDE-R Pin */
+#define D22IP_MEI2IP   4       /* MEI #2 Pin */
+#define D22IP_MEI1IP   0       /* MEI #1 Pin */
+#define D20IP          0x3128  /* 32bit */
+#define D20IP_XHCIIP   0
+#define D31IR          0x3140  /* 16bit */
+#define D30IR          0x3142  /* 16bit */
+#define D29IR          0x3144  /* 16bit */
+#define D28IR          0x3146  /* 16bit */
+#define D27IR          0x3148  /* 16bit */
+#define D26IR          0x314c  /* 16bit */
+#define D25IR          0x3150  /* 16bit */
+#define D22IR          0x315c  /* 16bit */
+#define D20IR          0x3160  /* 16bit */
+#define OIC            0x31fe  /* 16bit */
+
 #define SPI_FREQ_SWSEQ 0x3893
 #define SPI_DESC_COMP0 0x38b0
 #define SPI_FREQ_WR_ERA        0x38b4
 #define SOFT_RESET_CTRL 0x38f4
 #define SOFT_RESET_DATA 0x38f8
 
+#define DIR_ROUTE(a, b, c, d) \
+               (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
+                       ((b) << DIR_IBR) | ((a) << DIR_IAR))
+
 #define RC             0x3400  /* 32bit */
 #define HPTC           0x3404  /* 32bit */
 #define GCS            0x3410  /* 32bit */
@@ -142,6 +234,27 @@
 #define FD2            0x3428  /* 32bit */
 #define CG             0x341c  /* 32bit */
 
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS     ((1 << 0)|(1 << 26))
+#define PCH_DISABLE_P2P                (1 << 1)
+#define PCH_DISABLE_SATA1      (1 << 2)
+#define PCH_DISABLE_SMBUS      (1 << 3)
+#define PCH_DISABLE_HD_AUDIO   (1 << 4)
+#define PCH_DISABLE_EHCI2      (1 << 13)
+#define PCH_DISABLE_LPC                (1 << 14)
+#define PCH_DISABLE_EHCI1      (1 << 15)
+#define PCH_DISABLE_PCIE(x)    (1 << (16 + x))
+#define PCH_DISABLE_THERMAL    (1 << 24)
+#define PCH_DISABLE_SATA2      (1 << 25)
+#define PCH_DISABLE_XHCI       (1 << 27)
+
+/* Function Disable 2 RCBA 0x3428 */
+#define PCH_DISABLE_KT         (1 << 4)
+#define PCH_DISABLE_IDER       (1 << 3)
+#define PCH_DISABLE_MEI2       (1 << 2)
+#define PCH_DISABLE_MEI1       (1 << 1)
+#define PCH_ENABLE_DBDF                (1 << 0)
+
 /* ICH7 GPIOBASE */
 #define GPIO_USE_SEL   0x00
 #define GP_IO_SEL      0x04