Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...
[oweals/u-boot.git] / arch / x86 / dts / crownbay.dts
index d6dd0b49f0fac3a64f9ec4192c3a2ed431d2610f..f492c35875b65c39a43e155b0b449da8ecd54a4e 100644 (file)
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /dts-v1/;
@@ -11,6 +10,8 @@
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 /include/ "keyboard.dtsi"
+/include/ "pcspkr.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
@@ -19,7 +20,7 @@
        compatible = "intel,crownbay", "intel,queensbay";
 
        aliases {
-               spi0 = "/spi";
+               spi0 = &spi;
        };
 
        config {
 
        };
 
-       gpioa {
-               compatible = "intel,ich6-gpio";
-               u-boot,dm-pre-reloc;
-               reg = <0 0x20>;
-               bank-name = "A";
-       };
-
-       gpiob {
-               compatible = "intel,ich6-gpio";
-               u-boot,dm-pre-reloc;
-               reg = <0x20 0x20>;
-               bank-name = "B";
-       };
-
        chosen {
                /*
                 * By default the legacy superio serial port is used as the
                pch@1f,0 {
                        reg = <0x0000f800 0 0 0 0>;
                        compatible = "intel,pch7";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
 
                        irq-router {
-                               compatible = "intel,queensbay-irq-router";
+                               compatible = "intel,irq-router";
                                intel,pirq-config = "pci";
+                               intel,actl-addr = <0x58>;
                                intel,pirq-link = <0x60 8>;
                                intel,pirq-mask = <0xcee0>;
                                intel,pirq-routing = <
                                >;
                        };
 
-                       spi {
+                       spi: spi {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               compatible = "intel,ich-spi";
+                               compatible = "intel,ich7-spi";
                                spi-flash@0 {
                                        reg = <0>;
                                        compatible = "sst,25vf016b",
-                                               "spi-flash";
+                                               "jedec,spi-nor";
                                        memory-map = <0xffe00000 0x00200000>;
                                };
                        };
+
+                       gpioa {
+                               compatible = "intel,ich6-gpio";
+                               u-boot,dm-pre-reloc;
+                               reg = <0 0x20>;
+                               bank-name = "A";
+                       };
+
+                       gpiob {
+                               compatible = "intel,ich6-gpio";
+                               u-boot,dm-pre-reloc;
+                               reg = <0x20 0x20>;
+                               bank-name = "B";
+                       };
                };
        };