x86: Add Intel Bayley Bay board support

[oweals/u-boot.git] / arch / x86 / dts / crownbay.dts

diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index fbdeade0474f0d7db5e211ba79c18f9e60a8790d..3af9cc3d2606ec2a8adfbf39fa134727b17e742d 100644 (file)
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -6,8 +6,11 @@
 
 /dts-v1/;
 
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "rtc.dtsi"
 
 / {
        model = "Intel Crown Bay";
@@ -21,6 +24,26 @@
                silent_console = <0>;
        };
 
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "cpu-x86";
+                       reg = <0>;
+                       intel,apic-id = <0>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "cpu-x86";
+                       reg = <1>;
+                       intel,apic-id = <1>;
+               };
+
+       };
+
        gpioa {
                compatible = "intel,ich6-gpio";
                u-boot,dm-pre-reloc;
@@ -67,8 +90,12 @@
        pci {
                #address-cells = <3>;
                #size-cells = <2>;
-               compatible = "intel,pci";
+               compatible = "pci-x86";
                device_type = "pci";
+               u-boot,dm-pre-reloc;
+               ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
+                         0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
+                         0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 
                pcie@17,0 {
                        #address-cells = <3>;
@@ -135,6 +162,70 @@
                                };
                        };
                };
+
+               irq-router@1f,0 {
+                       reg = <0x0000f800 0 0 0 0>;
+                       compatible = "intel,irq-router";
+                       intel,pirq-config = "pci";
+                       intel,pirq-link = <0x60 8>;
+                       intel,pirq-mask = <0xdee0>;
+                       intel,pirq-routing = <
+                               /* TunnelCreek PCI devices */
+                               PCI_BDF(0, 2, 0) INTA PIRQE
+                               PCI_BDF(0, 3, 0) INTA PIRQF
+                               PCI_BDF(0, 23, 0) INTA PIRQA
+                               PCI_BDF(0, 23, 0) INTB PIRQB
+                               PCI_BDF(0, 23, 0) INTC PIRQC
+                               PCI_BDF(0, 23, 0) INTD PIRQD
+                               PCI_BDF(0, 24, 0) INTA PIRQB
+                               PCI_BDF(0, 24, 0) INTB PIRQC
+                               PCI_BDF(0, 24, 0) INTC PIRQD
+                               PCI_BDF(0, 24, 0) INTD PIRQA
+                               PCI_BDF(0, 25, 0) INTA PIRQC
+                               PCI_BDF(0, 25, 0) INTB PIRQD
+                               PCI_BDF(0, 25, 0) INTC PIRQA
+                               PCI_BDF(0, 25, 0) INTD PIRQB
+                               PCI_BDF(0, 26, 0) INTA PIRQD
+                               PCI_BDF(0, 26, 0) INTB PIRQA
+                               PCI_BDF(0, 26, 0) INTC PIRQB
+                               PCI_BDF(0, 26, 0) INTD PIRQC
+                               PCI_BDF(0, 27, 0) INTA PIRQG
+                               /*
+                                * Topcliff PCI devices
+                                *
+                                * Note on the Crown Bay board, Topcliff chipset
+                                * is connected to TunnelCreek PCIe port 0, so
+                                * its bus number is 1 for its PCIe port and 2
+                                * for its PCI devices per U-Boot current PCI
+                                * bus enumeration algorithm.
+                                */
+                               PCI_BDF(1, 0, 0) INTA PIRQA
+                               PCI_BDF(2, 0, 1) INTA PIRQA
+                               PCI_BDF(2, 0, 2) INTA PIRQA
+                               PCI_BDF(2, 2, 0) INTB PIRQD
+                               PCI_BDF(2, 2, 1) INTB PIRQD
+                               PCI_BDF(2, 2, 2) INTB PIRQD
+                               PCI_BDF(2, 2, 3) INTB PIRQD
+                               PCI_BDF(2, 2, 4) INTB PIRQD
+                               PCI_BDF(2, 4, 0) INTC PIRQC
+                               PCI_BDF(2, 4, 1) INTC PIRQC
+                               PCI_BDF(2, 6, 0) INTD PIRQB
+                               PCI_BDF(2, 8, 0) INTA PIRQA
+                               PCI_BDF(2, 8, 1) INTA PIRQA
+                               PCI_BDF(2, 8, 2) INTA PIRQA
+                               PCI_BDF(2, 8, 3) INTA PIRQA
+                               PCI_BDF(2, 10, 0) INTB PIRQD
+                               PCI_BDF(2, 10, 1) INTB PIRQD
+                               PCI_BDF(2, 10, 2) INTB PIRQD
+                               PCI_BDF(2, 10, 3) INTB PIRQD
+                               PCI_BDF(2, 10, 4) INTB PIRQD
+                               PCI_BDF(2, 12, 0) INTC PIRQC
+                               PCI_BDF(2, 12, 1) INTC PIRQC
+                               PCI_BDF(2, 12, 2) INTC PIRQC
+                               PCI_BDF(2, 12, 3) INTC PIRQC
+                               PCI_BDF(2, 12, 4) INTC PIRQC
+                       >;
+               };
        };
 
 };