Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / x86 / dts / cougarcanyon2.dts

diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts
index d41556638ce5cbd16e7cfcf53c4df065bc942277..c6ba811e059e58b5a1594174db83c7e912035f17 100644 (file)
--- a/arch/x86/dts/cougarcanyon2.dts
+++ b/arch/x86/dts/cougarcanyon2.dts
@@ -1,14 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /dts-v1/;
 
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 /include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
@@ -28,6 +30,39 @@
                stdout-path = "/serial";
        };
 
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "intel,core-gen3";
+                       reg = <0>;
+                       intel,apic-id = <0>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "intel,core-gen3";
+                       reg = <1>;
+                       intel,apic-id = <1>;
+               };
+
+               cpu@2 {
+                       device_type = "cpu";
+                       compatible = "intel,core-gen3";
+                       reg = <2>;
+                       intel,apic-id = <2>;
+               };
+
+               cpu@3 {
+                       device_type = "cpu";
+                       compatible = "intel,core-gen3";
+                       reg = <3>;
+                       intel,apic-id = <3>;
+               };
+       };
+
        microcode {
                update@0 {
 #include "microcode/m12306a2_00000008.dtsi"
@@ -67,13 +102,59 @@
                        #address-cells = <1>;
                        #size-cells = <1>;
 
+                       irq-router {
+                               compatible = "intel,irq-router";
+                               intel,pirq-config = "pci";
+                               intel,actl-8bit;
+                               intel,actl-addr = <0x44>;
+                               intel,pirq-link = <0x60 8>;
+                               intel,pirq-regmap = <
+                                       PIRQA 0
+                                       PIRQB 1
+                                       PIRQC 2
+                                       PIRQD 3
+                                       PIRQE 8
+                                       PIRQF 9
+                                       PIRQG 10
+                                       PIRQH 11
+                               >;
+                               intel,pirq-mask = <0xcee0>;
+                               intel,pirq-routing = <
+                                       /* Panther Point PCI devices */
+                                       PCI_BDF(0, 2, 0) INTA PIRQA
+                                       PCI_BDF(0, 20, 0) INTA PIRQA
+                                       PCI_BDF(0, 22, 0) INTA PIRQA
+                                       PCI_BDF(0, 22, 1) INTB PIRQB
+                                       PCI_BDF(0, 22, 2) INTC PIRQC
+                                       PCI_BDF(0, 22, 3) INTD PIRQD
+                                       PCI_BDF(0, 25, 0) INTA PIRQA
+                                       PCI_BDF(0, 26, 0) INTA PIRQA
+                                       PCI_BDF(0, 27, 0) INTB PIRQA
+                                       PCI_BDF(0, 28, 0) INTA PIRQA
+                                       PCI_BDF(0, 28, 1) INTB PIRQB
+                                       PCI_BDF(0, 28, 2) INTC PIRQC
+                                       PCI_BDF(0, 28, 3) INTD PIRQD
+                                       PCI_BDF(0, 28, 4) INTA PIRQA
+                                       PCI_BDF(0, 28, 5) INTB PIRQB
+                                       PCI_BDF(0, 28, 6) INTC PIRQC
+                                       PCI_BDF(0, 28, 7) INTD PIRQD
+                                       PCI_BDF(0, 29, 0) INTA PIRQA
+                                       PCI_BDF(0, 31, 2) INTB PIRQB
+                                       PCI_BDF(0, 31, 3) INTC PIRQC
+                                       PCI_BDF(0, 31, 5) INTB PIRQB
+                                       PCI_BDF(0, 31, 6) INTC PIRQC
+                               >;
+                       };
+
                        spi0: spi {
                                #address-cells = <1>;
                                #size-cells = <0>;
                                compatible = "intel,ich9-spi";
+                               intel,spi-lock-down;
+
                                spi-flash@0 {
                                        reg = <0>;
-                                       compatible = "winbond,w25q64bv", "spi-flash";
+                                       compatible = "winbond,w25q64bv", "jedec,spi-nor";
                                        memory-map = <0xff800000 0x00800000>;
                                };
                        };