x86: Add Intel Bayley Bay board support

[oweals/u-boot.git] / arch / x86 / dts / chromebook_link.dts

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index cdbdb6827e432831992d83a69a98d93b4502f20f..ad390bf11721a3b161c3b55a1c517ddf1e55eb5b 100644 (file)
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -2,13 +2,14 @@
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "rtc.dtsi"
 
 / {
        model = "Google Link";
        compatible = "google,link", "intel,celeron-ivybridge";
 
        aliases {
-               spi0 = "/spi";
+               spi0 = "/pci/pch/spi";
        };
 
        config {
@@ -151,26 +152,6 @@
                };
        };
 
-       spi {
-               #address-cells = <1>;
-               #size-cells = <0>;
-               compatible = "intel,ich-spi";
-               spi-flash@0 {
-                       #size-cells = <1>;
-                       #address-cells = <1>;
-                       reg = <0>;
-                       compatible = "winbond,w25q64", "spi-flash";
-                       memory-map = <0xff800000 0x00800000>;
-                       rw-mrc-cache {
-                               label = "rw-mrc-cache";
-                               /* Alignment: 4k (for updating) */
-                               reg = <0x003e0000 0x00010000>;
-                               type = "wiped";
-                               wipe-value = [ff];
-                       };
-               };
-       };
-
        pci {
                compatible = "intel,pci-ivybridge", "pci-x86";
                #address-cells = <3>;
@@ -199,8 +180,10 @@
                        intel,pch-backlight = <0x04000000>;
                };
 
-               lpc {
-                       compatible = "intel,lpc";
+               pch {
+                       reg = <0x0000f800 0 0 0 0>;
+                       compatible = "intel,bd82x6x", "intel,pch";
+                       u-boot,dm-pre-reloc;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        gen-dec = <0x800 0xfc 0x900 0xfc>;
@@ -211,17 +194,44 @@
                                                1 0 0 0 0 0 0 0>;
                        /* Enable EC SMI source */
                        intel,alt-gp-smi-enable = <0x0100>;
+                       spi {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "intel,ich-spi";
+                               spi-flash@0 {
+                                       #size-cells = <1>;
+                                       #address-cells = <1>;
+                                       reg = <0>;
+                                       compatible = "winbond,w25q64",
+                                                       "spi-flash";
+                                       memory-map = <0xff800000 0x00800000>;
+                                       rw-mrc-cache {
+                                               label = "rw-mrc-cache";
+                                               reg = <0x003e0000 0x00010000>;
+                                               type = "wiped";
+                                               wipe-value = [ff];
+                                       };
+                               };
+                       };
 
-                       cros-ec@200 {
-                               compatible = "google,cros-ec";
-                               reg = <0x204 1 0x200 1 0x880 0x80>;
-
-                               /* Describes the flash memory within the EC */
+                       lpc {
+                               compatible = "intel,bd82x6x-lpc";
                                #address-cells = <1>;
-                               #size-cells = <1>;
-                               flash@8000000 {
-                                       reg = <0x08000000 0x20000>;
-                                       erase-value = <0xff>;
+                               #size-cells = <0>;
+                               cros-ec@200 {
+                                       compatible = "google,cros-ec";
+                                       reg = <0x204 1 0x200 1 0x880 0x80>;
+
+                                       /*
+                                        * Describes the flash memory within
+                                        * the EC
+                                        */
+                                       #address-cells = <1>;
+                                       #size-cells = <1>;
+                                       flash@8000000 {
+                                               reg = <0x08000000 0x20000>;
+                                               erase-value = <0xff>;
+                                       };
                                };
                        };
                };