arm: mach-k3: Enable dcache in SPL

[oweals/u-boot.git] / arch / x86 / cpu / turbo.c

diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c
index c0bff75c4f16de23031c2aeef52cee0e5f4178f1..be468d2b2cac5f5b28ce83effb6eacce0e0a46a1 100644 (file)
--- a/arch/x86/cpu/turbo.c
+++ b/arch/x86/cpu/turbo.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * From Coreboot file of the same name
  *
  * Copyright (C) 2011 The Chromium Authors.
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 #include <common.h>
@@ -61,8 +60,8 @@ int turbo_get_state(void)
        cpuid_regs = cpuid(CPUID_LEAF_PM);
        turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE);
 
-       msr = msr_read(MSR_IA32_MISC_ENABLES);
-       turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO);
+       msr = msr_read(MSR_IA32_MISC_ENABLE);
+       turbo_en = !(msr.hi & MISC_DISABLE_TURBO);
 
        if (!turbo_cap && turbo_en) {
                /* Unavailable */
@@ -87,9 +86,9 @@ void turbo_enable(void)
        /* Only possible if turbo is available but hidden */
        if (turbo_get_state() == TURBO_DISABLED) {
                /* Clear Turbo Disable bit in Misc Enables */
-               msr = msr_read(MSR_IA32_MISC_ENABLES);
-               msr.hi &= ~H_MISC_DISABLE_TURBO;
-               msr_write(MSR_IA32_MISC_ENABLES, msr);
+               msr = msr_read(MSR_IA32_MISC_ENABLE);
+               msr.hi &= ~MISC_DISABLE_TURBO;
+               msr_write(MSR_IA32_MISC_ENABLE, msr);
 
                /* Update cached turbo state */
                set_global_turbo_state(TURBO_ENABLED);