x86: tnc: Use DM PCI API in disable_igd()

[oweals/u-boot.git] / arch / x86 / cpu / queensbay / tnc.c

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 933d189f05e23819c24502f02448f126be832316..38082c4a779e3930781dcf53acacffb78003c494 100644 (file)
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -5,26 +5,33 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <pci.h>
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/arch/device.h>
 #include <asm/arch/tnc.h>
 #include <asm/fsp/fsp_support.h>
 #include <asm/processor.h>
 
-static void unprotect_spi_flash(void)
+static int __maybe_unused disable_igd(void)
 {
-       u32 bc;
+       struct udevice *igd, *sdvo;
+       int ret;
 
-       bc = x86_pci_read_config32(TNC_LPC, 0xd8);
-       bc |= 0x1;      /* unprotect the flash */
-       x86_pci_write_config32(TNC_LPC, 0xd8, bc);
-}
+       ret = dm_pci_bus_find_bdf(TNC_IGD, &igd);
+       if (ret)
+               return ret;
+       if (!igd)
+               return 0;
+
+       ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo);
+       if (ret)
+               return ret;
+       if (!sdvo)
+               return 0;
 
-static void __maybe_unused disable_igd(void)
-{
        /*
         * According to Atom E6xx datasheet, setting VGA Disable (bit17)
         * of Graphics Controller register (offset 0x50) prevents IGD
@@ -43,8 +50,10 @@ static void __maybe_unused disable_igd(void)
         * two devices will be completely disabled (invisible in the PCI
         * configuration space) unless a system reset is performed.
         */
-       x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE);
-       x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE);
+       dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE);
+       dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE);
+
+       return 0;
 }
 
 int arch_cpu_init(void)
@@ -52,9 +61,6 @@ int arch_cpu_init(void)
        int ret;
 
        post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
-       timer_set_base(rdtsc());
-#endif
 
        ret = x86_cpu_init_f();
        if (ret)
@@ -65,53 +71,11 @@ int arch_cpu_init(void)
 
 int arch_early_init_r(void)
 {
+       int ret = 0;
+
 #ifdef CONFIG_DISABLE_IGD
-       disable_igd();
+       ret = disable_igd();
 #endif
 
-       return 0;
-}
-
-void cpu_irq_init(void)
-{
-       struct tnc_rcba *rcba;
-       u32 base;
-
-       base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
-       base &= ~MEM_BAR_EN;
-       rcba = (struct tnc_rcba *)base;
-
-       /* Make sure all internal PCI devices are using INTA */
-       writel(INTA, &rcba->d02ip);
-       writel(INTA, &rcba->d03ip);
-       writel(INTA, &rcba->d27ip);
-       writel(INTA, &rcba->d31ip);
-       writel(INTA, &rcba->d23ip);
-       writel(INTA, &rcba->d24ip);
-       writel(INTA, &rcba->d25ip);
-       writel(INTA, &rcba->d26ip);
-
-       /*
-        * Route TunnelCreek PCI device interrupt pin to PIRQ
-        *
-        * Since PCIe downstream ports received INTx are routed to PIRQ
-        * A/B/C/D directly and not configurable, we have to route PCIe
-        * root ports' INTx to PIRQ A/B/C/D as well. For other devices
-        * on TunneCreek, route them to PIRQ E/F/G/H.
-        */
-       writew(PIRQE, &rcba->d02ir);
-       writew(PIRQF, &rcba->d03ir);
-       writew(PIRQG, &rcba->d27ir);
-       writew(PIRQH, &rcba->d31ir);
-       writew(PIRQA, &rcba->d23ir);
-       writew(PIRQB, &rcba->d24ir);
-       writew(PIRQC, &rcba->d25ir);
-       writew(PIRQD, &rcba->d26ir);
-}
-
-int arch_misc_init(void)
-{
-       unprotect_spi_flash();
-
-       return pirq_init();
+       return ret;
 }