x86: tnc: Use DM PCI API in disable_igd()

[oweals/u-boot.git] / arch / x86 / cpu / queensbay / tnc.c

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 8637cdca2dd4679f99bb3c56cec784cf03e7bfd1..38082c4a779e3930781dcf53acacffb78003c494 100644 (file)
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -5,68 +5,77 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <pci.h>
 #include <asm/io.h>
-#include <asm/pci.h>
+#include <asm/irq.h>
 #include <asm/post.h>
+#include <asm/arch/device.h>
 #include <asm/arch/tnc.h>
-#include <asm/arch/fsp/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
 #include <asm/processor.h>
 
-static void unprotect_spi_flash(void)
+static int __maybe_unused disable_igd(void)
 {
-       u32 bc;
-
-       bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
-       bc |= 0x1;      /* unprotect the flash */
-       pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
-}
-
-int arch_cpu_init(void)
-{
-       struct pci_controller *hose;
+       struct udevice *igd, *sdvo;
        int ret;
 
-       post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
-       timer_set_base(rdtsc());
-#endif
-
-       ret = x86_cpu_init_f();
+       ret = dm_pci_bus_find_bdf(TNC_IGD, &igd);
        if (ret)
                return ret;
+       if (!igd)
+               return 0;
 
-       ret = pci_early_init_hose(&hose);
+       ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo);
        if (ret)
                return ret;
+       if (!sdvo)
+               return 0;
 
-       unprotect_spi_flash();
+       /*
+        * According to Atom E6xx datasheet, setting VGA Disable (bit17)
+        * of Graphics Controller register (offset 0x50) prevents IGD
+        * (D2:F0) from reporting itself as a VGA display controller
+        * class in the PCI configuration space, and should also prevent
+        * it from responding to VGA legacy memory range and I/O addresses.
+        *
+        * However test result shows that with just VGA Disable bit set and
+        * a PCIe graphics card connected to one of the PCIe controllers on
+        * the E6xx, accessing the VGA legacy space still causes system hang.
+        * After a number of attempts, it turns out besides VGA Disable bit,
+        * the SDVO (D3:F0) device should be disabled to make it work.
+        *
+        * To simplify, use the Function Disable register (offset 0xc4)
+        * to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
+        * two devices will be completely disabled (invisible in the PCI
+        * configuration space) unless a system reset is performed.
+        */
+       dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE);
+       dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE);
 
        return 0;
 }
 
-int print_cpuinfo(void)
+int arch_cpu_init(void)
 {
-       post_code(POST_CPU_INFO);
-       return default_print_cpuinfo();
-}
+       int ret;
 
-void reset_cpu(ulong addr)
-{
-       /* cold reset */
-       outb(0x06, PORT_RESET);
+       post_code(POST_CPU_INIT);
+
+       ret = x86_cpu_init_f();
+       if (ret)
+               return ret;
+
+       return 0;
 }
 
-void board_final_cleanup(void)
+int arch_early_init_r(void)
 {
-       u32 status;
+       int ret = 0;
 
-       /* call into FspNotify */
-       debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
-       status = fsp_notify(NULL, INIT_PHASE_BOOT);
-       if (status != FSP_SUCCESS)
-               debug("fail, error code %x\n", status);
-       else
-               debug("OK\n");
+#ifdef CONFIG_DISABLE_IGD
+       ret = disable_igd();
+#endif
 
-       return;
+       return ret;
 }