#include <asm/irq.h>
#include <asm/pci.h>
#include <asm/pirq_routing.h>
+#include <asm/tables.h>
DECLARE_GLOBAL_DATA_PTR;
-static struct irq_router irq_router;
-static struct irq_routing_table *pirq_routing_table;
-
-bool pirq_check_irq_routed(int link, u8 irq)
+bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
{
+ struct irq_router *priv = dev_get_priv(dev);
u8 pirq;
- int base = irq_router.link_base;
+ int base = priv->link_base;
- if (irq_router.config == PIRQ_VIA_PCI)
- pirq = x86_pci_read_config8(irq_router.bdf,
- LINK_N2V(link, base));
+ if (priv->config == PIRQ_VIA_PCI)
+ dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
else
- pirq = readb(irq_router.ibase + LINK_N2V(link, base));
+ pirq = readb((uintptr_t)priv->ibase + LINK_N2V(link, base));
pirq &= 0xf;
return pirq == irq ? true : false;
}
-int pirq_translate_link(int link)
+int pirq_translate_link(struct udevice *dev, int link)
{
- return LINK_V2N(link, irq_router.link_base);
+ struct irq_router *priv = dev_get_priv(dev);
+
+ return LINK_V2N(link, priv->link_base);
}
-void pirq_assign_irq(int link, u8 irq)
+void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
{
- int base = irq_router.link_base;
+ struct irq_router *priv = dev_get_priv(dev);
+ int base = priv->link_base;
/* IRQ# 0/1/2/8/13 are reserved */
if (irq < 3 || irq == 8 || irq == 13)
return;
- if (irq_router.config == PIRQ_VIA_PCI)
- x86_pci_write_config8(irq_router.bdf,
- LINK_N2V(link, base), irq);
+ if (priv->config == PIRQ_VIA_PCI)
+ dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq);
else
- writeb(irq, irq_router.ibase + LINK_N2V(link, base));
+ writeb(irq, (uintptr_t)priv->ibase + LINK_N2V(link, base));
}
static struct irq_info *check_dup_entry(struct irq_info *slot_base,
return (i == entry_num) ? NULL : slot;
}
-static inline void fill_irq_info(struct irq_info *slot, int bus, int device,
- int pin, int pirq)
+static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot,
+ int bus, int device, int pin, int pirq)
{
slot->bus = bus;
slot->devfn = (device << 3) | 0;
- slot->irq[pin - 1].link = LINK_N2V(pirq, irq_router.link_base);
- slot->irq[pin - 1].bitmap = irq_router.irq_mask;
+ slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base);
+ slot->irq[pin - 1].bitmap = priv->irq_mask;
}
static int create_pirq_routing_table(struct udevice *dev)
{
+ struct irq_router *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- struct fdt_pci_addr addr;
int node;
int len, count;
const u32 *cell;
struct irq_routing_table *rt;
struct irq_info *slot, *slot_base;
int irq_entries = 0;
- int parent;
int i;
int ret;
- node = dev->of_offset;
- parent = dev->parent->of_offset;
- ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
- "reg", &addr);
- if (ret)
- return ret;
+ node = dev_of_offset(dev);
/* extract the bdf from fdt_pci_addr */
- irq_router.bdf = addr.phys_hi & 0xffff00;
+ priv->bdf = dm_pci_get_bdf(dev->parent);
- ret = fdt_find_string(blob, node, "intel,pirq-config", "pci");
+ ret = fdt_stringlist_search(blob, node, "intel,pirq-config", "pci");
if (!ret) {
- irq_router.config = PIRQ_VIA_PCI;
+ priv->config = PIRQ_VIA_PCI;
} else {
- ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase");
+ ret = fdt_stringlist_search(blob, node, "intel,pirq-config",
+ "ibase");
if (!ret)
- irq_router.config = PIRQ_VIA_IBASE;
+ priv->config = PIRQ_VIA_IBASE;
else
return -EINVAL;
}
ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
if (ret == -1)
return ret;
- irq_router.link_base = ret;
+ priv->link_base = ret;
+
+ priv->irq_mask = fdtdec_get_int(blob, node,
+ "intel,pirq-mask", PIRQ_BITMAP);
- irq_router.irq_mask = fdtdec_get_int(blob, node,
- "intel,pirq-mask", PIRQ_BITMAP);
+ if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
+ /* Reserve IRQ9 for SCI */
+ priv->irq_mask &= ~(1 << 9);
+ }
- if (irq_router.config == PIRQ_VIA_IBASE) {
+ if (priv->config == PIRQ_VIA_IBASE) {
int ibase_off;
ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
* 2) memory range decoding is enabled.
* Hence we don't do any santify test here.
*/
- irq_router.ibase = x86_pci_read_config32(irq_router.bdf,
- ibase_off);
- irq_router.ibase &= ~0xf;
+ dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
+ priv->ibase &= ~0xf;
}
+ priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
+ priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
+
cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
if (!cell || len % sizeof(struct pirq_routing))
return -EINVAL;
/* Populate the PIRQ table fields */
rt->signature = PIRQ_SIGNATURE;
rt->version = PIRQ_VERSION;
- rt->rtr_bus = PCI_BUS(irq_router.bdf);
- rt->rtr_devfn = (PCI_DEV(irq_router.bdf) << 3) |
- PCI_FUNC(irq_router.bdf);
+ rt->rtr_bus = PCI_BUS(priv->bdf);
+ rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf);
rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
* routing information in the device tree.
*/
if (slot->irq[pr.pin - 1].link !=
- LINK_N2V(pr.pirq, irq_router.link_base))
+ LINK_N2V(pr.pirq, priv->link_base))
debug("WARNING: Inconsistent PIRQ routing information\n");
continue;
}
slot = slot_base + irq_entries++;
}
debug("writing INT%c\n", 'A' + pr.pin - 1);
- fill_irq_info(slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin,
- pr.pirq);
+ fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
+ pr.pin, pr.pirq);
}
rt->size = irq_entries * sizeof(struct irq_info) + 32;
- pirq_routing_table = rt;
+ /* Fix up the table checksum */
+ rt->checksum = table_compute_checksum(rt, rt->size);
+
+ gd->arch.pirq_routing_table = rt;
return 0;
}
+static void irq_enable_sci(struct udevice *dev)
+{
+ struct irq_router *priv = dev_get_priv(dev);
+
+ if (priv->actl_8bit) {
+ /* Bit7 must be turned on to enable ACPI */
+ dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
+ } else {
+ /* Write 0 to enable SCI on IRQ9 */
+ if (priv->config == PIRQ_VIA_PCI)
+ dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
+ else
+ writel(0, (uintptr_t)priv->ibase + priv->actl_addr);
+ }
+}
+
int irq_router_common_init(struct udevice *dev)
{
int ret;
return ret;
}
/* Route PIRQ */
- pirq_route_irqs(pirq_routing_table->slots,
- get_irq_slot_count(pirq_routing_table));
+ pirq_route_irqs(dev, gd->arch.pirq_routing_table->slots,
+ get_irq_slot_count(gd->arch.pirq_routing_table));
+
+ if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
+ irq_enable_sci(dev);
return 0;
}
return irq_router_common_init(dev);
}
-u32 write_pirq_routing_table(u32 addr)
+ulong write_pirq_routing_table(ulong addr)
{
- if (!pirq_routing_table)
+ if (!gd->arch.pirq_routing_table)
return addr;
- return copy_pirq_routing_table(addr, pirq_routing_table);
+ return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table);
}
static const struct udevice_id irq_router_ids[] = {
.id = UCLASS_IRQ,
.of_match = irq_router_ids,
.probe = irq_router_probe,
+ .priv_auto_alloc_size = sizeof(struct irq_router),
};
UCLASS_DRIVER(irq) = {
projects / oweals / u-boot.git / blobdiff