x86: broadwell: Correct I/O APIC ID

[oweals/u-boot.git] / arch / x86 / cpu / irq.c

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index fea6f65c7afddd1c694fa843adae17e921d23dde..df3cd0abc7771bef450f70c458ad13613d2162e4 100644 (file)
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -13,6 +13,7 @@
 #include <asm/irq.h>
 #include <asm/pci.h>
 #include <asm/pirq_routing.h>
+#include <asm/tables.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -25,7 +26,7 @@ bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
        int base = priv->link_base;
 
        if (priv->config == PIRQ_VIA_PCI)
-               pirq = x86_pci_read_config8(priv->bdf, LINK_N2V(link, base));
+               dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
        else
                pirq = readb(priv->ibase + LINK_N2V(link, base));
 
@@ -55,7 +56,7 @@ void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
                return;
 
        if (priv->config == PIRQ_VIA_PCI)
-               x86_pci_write_config8(priv->bdf, LINK_N2V(link, base), irq);
+               dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq);
        else
                writeb(irq, priv->ibase + LINK_N2V(link, base));
 }
@@ -121,6 +122,11 @@ static int create_pirq_routing_table(struct udevice *dev)
        priv->irq_mask = fdtdec_get_int(blob, node,
                                        "intel,pirq-mask", PIRQ_BITMAP);
 
+       if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
+               /* Reserve IRQ9 for SCI */
+               priv->irq_mask &= ~(1 << 9);
+       }
+
        if (priv->config == PIRQ_VIA_IBASE) {
                int ibase_off;
 
@@ -138,10 +144,13 @@ static int create_pirq_routing_table(struct udevice *dev)
                 *   2) memory range decoding is enabled.
                 * Hence we don't do any santify test here.
                 */
-               priv->ibase = x86_pci_read_config32(priv->bdf, ibase_off);
+               dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
                priv->ibase &= ~0xf;
        }
 
+       priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
+       priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
+
        cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
        if (!cell || len % sizeof(struct pirq_routing))
                return -EINVAL;
@@ -206,11 +215,30 @@ static int create_pirq_routing_table(struct udevice *dev)
 
        rt->size = irq_entries * sizeof(struct irq_info) + 32;
 
+       /* Fix up the table checksum */
+       rt->checksum = table_compute_checksum(rt, rt->size);
+
        pirq_routing_table = rt;
 
        return 0;
 }
 
+static void irq_enable_sci(struct udevice *dev)
+{
+       struct irq_router *priv = dev_get_priv(dev);
+
+       if (priv->actl_8bit) {
+               /* Bit7 must be turned on to enable ACPI */
+               dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
+       } else {
+               /* Write 0 to enable SCI on IRQ9 */
+               if (priv->config == PIRQ_VIA_PCI)
+                       dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
+               else
+                       writel(0, priv->ibase + priv->actl_addr);
+       }
+}
+
 int irq_router_common_init(struct udevice *dev)
 {
        int ret;
@@ -224,6 +252,9 @@ int irq_router_common_init(struct udevice *dev)
        pirq_route_irqs(dev, pirq_routing_table->slots,
                        get_irq_slot_count(pirq_routing_table));
 
+       if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
+               irq_enable_sci(dev);
+
        return 0;
 }