Merge branch 'master' of git://git.denx.de/u-boot-x86

[oweals/u-boot.git] / arch / x86 / cpu / cpu.c

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 8102fb9519810b0b2a753f3b7c4c75f1fb39dfe6..fabfbd1bf7f9f5deb40ffdcf04f81ec42eb6c52b 100644 (file)
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -90,6 +90,36 @@ static void load_gdt(const u64 *boot_gdt, u16 num_entries)
        asm volatile("lgdtl %0\n" : : "m" (gdt));
 }
 
+void setup_gdt(gd_t *id, u64 *gdt_addr)
+{
+       /* CS: code, read/execute, 4 GB, base 0 */
+       gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
+
+       /* DS: data, read/write, 4 GB, base 0 */
+       gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
+
+       /* FS: data, read/write, 4 GB, base (Global Data Pointer) */
+       gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, (ulong)id, 0xfffff);
+
+       /* 16-bit CS: code, read/execute, 64 kB, base 0 */
+       gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff);
+
+       /* 16-bit DS: data, read/write, 64 kB, base 0 */
+       gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff);
+
+       load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
+       load_ds(X86_GDT_ENTRY_32BIT_DS);
+       load_es(X86_GDT_ENTRY_32BIT_DS);
+       load_gs(X86_GDT_ENTRY_32BIT_DS);
+       load_ss(X86_GDT_ENTRY_32BIT_DS);
+       load_fs(X86_GDT_ENTRY_32BIT_FS);
+}
+
+int __weak x86_cleanup_before_linux(void)
+{
+       return 0;
+}
+
 int x86_cpu_init_f(void)
 {
        const u32 em_rst = ~X86_CR0_EM;
@@ -108,6 +138,14 @@ int x86_cpu_init_f(void)
 int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
 
 int x86_cpu_init_r(void)
+{
+       /* Initialize core interrupt and exception functionality of CPU */
+       cpu_init_interrupts();
+       return 0;
+}
+int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
+
+void x86_enable_caches(void)
 {
        const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
 
@@ -116,34 +154,16 @@ int x86_cpu_init_r(void)
            "andl       %0, %%eax\n"
            "movl       %%eax, %%cr0\n"
            "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
+}
+void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
 
-       /*
-        * There are machines which are known to not boot with the GDT
-        * being 8-byte unaligned. Intel recommends 16 byte alignment
-        */
-       static const u64 boot_gdt[] __aligned(16) = {
-               /* CS: code, read/execute, 4 GB, base 0 */
-               [X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff),
-               /* DS: data, read/write, 4 GB, base 0 */
-               [X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff),
-               /* 16-bit CS: code, read/execute, 64 kB, base 0 */
-               [X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff),
-               /* 16-bit DS: data, read/write, 64 kB, base 0 */
-               [X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff),
-       };
-
-       load_gdt(boot_gdt, X86_GDT_NUM_ENTRIES);
-       load_ds(X86_GDT_ENTRY_32BIT_DS);
-       load_es(X86_GDT_ENTRY_32BIT_DS);
-       load_fs(X86_GDT_ENTRY_32BIT_DS);
-       load_gs(X86_GDT_ENTRY_32BIT_DS);
-       load_ss(X86_GDT_ENTRY_32BIT_DS);
+int x86_init_cache(void)
+{
+       enable_caches();
 
-       /* Initialize core interrupt and exception functionality of CPU */
-       cpu_init_interrupts();
        return 0;
 }
-int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
+int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {