#include <errno.h>
#include <malloc.h>
#include <asm/control_regs.h>
+#include <asm/coreboot_tables.h>
#include <asm/cpu.h>
#include <asm/lapic.h>
+#include <asm/microcode.h>
#include <asm/mp.h>
+#include <asm/mrccache.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
#include <asm/post.h>
* List of cpu vendor strings along with their normalized
* id values.
*/
-static struct {
+static const struct {
int vendor;
const char *name;
} x86_vendors[] = {
c->x86_model += ((tfms >> 16) & 0xF) << 4;
}
+u32 cpu_get_family_model(void)
+{
+ return gd->arch.x86_device & 0x0fff0ff0;
+}
+
+u32 cpu_get_stepping(void)
+{
+ return gd->arch.x86_mask;
+}
+
int x86_cpu_init_f(void)
{
const u32 em_rst = ~X86_CR0_EM;
}
}
+#ifdef CONFIG_I8254_TIMER
+ /* Set up the i8254 timer if required */
+ i8254_init();
+#endif
+
return 0;
}
__weak void reset_cpu(ulong addr)
{
/* Do a hard reset through the chipset's reset control register */
- outb(SYS_RST | RST_CPU, PORT_RESET);
+ outb(SYS_RST | RST_CPU, IO_PORT_RESET);
for (;;)
cpu_hlt();
}
void x86_full_reset(void)
{
- outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
+ outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
}
int dcache_status(void)
}
#ifndef CONFIG_SYS_COREBOOT
+/*
+ * Implement a weak default function for boards that optionally
+ * need to clean up the system before jumping to the kernel.
+ */
+__weak void board_final_cleanup(void)
+{
+}
+
int last_stage_init(void)
{
write_tables();
+ board_final_cleanup();
+
return 0;
}
#endif
}
#endif
-__weak int x86_init_cpus(void)
+static int x86_init_cpus(void)
{
#ifdef CONFIG_SMP
debug("Init additional CPUs\n");
int cpu_init_r(void)
{
- if (ll_boot_init())
- return x86_init_cpus();
+ struct udevice *dev;
+ int ret;
+
+ if (!ll_boot_init())
+ return 0;
+
+ ret = x86_init_cpus();
+ if (ret)
+ return ret;
+
+ /*
+ * Set up the northbridge, PCH and LPC if available. Note that these
+ * may have had some limited pre-relocation init if they were probed
+ * before relocation, but this is post relocation.
+ */
+ uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
+ uclass_first_device(UCLASS_PCH, &dev);
+ uclass_first_device(UCLASS_LPC, &dev);
+
+ return 0;
+}
+
+#ifndef CONFIG_EFI_STUB
+int reserve_arch(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+ mrccache_reserve();
+#endif
+
+#ifdef CONFIG_SEABIOS
+ high_table_reserve();
+#endif
return 0;
}
+#endif