#include <errno.h>
#include <malloc.h>
#include <asm/control_regs.h>
+#include <asm/coreboot_tables.h>
#include <asm/cpu.h>
#include <asm/lapic.h>
+#include <asm/microcode.h>
#include <asm/mp.h>
+#include <asm/mrccache.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
#include <asm/post.h>
* List of cpu vendor strings along with their normalized
* id values.
*/
-static struct {
+static const struct {
int vendor;
const char *name;
} x86_vendors[] = {
asm volatile("lgdtl %0\n" : : "m" (gdt));
}
-void setup_gdt(gd_t *id, u64 *gdt_addr)
+void arch_setup_gd(gd_t *new_gd)
{
- id->arch.gdt = gdt_addr;
- /* CS: code, read/execute, 4 GB, base 0 */
+ u64 *gdt_addr;
+
+ gdt_addr = new_gd->arch.gdt;
+
+ /*
+ * CS: code, read/execute, 4 GB, base 0
+ *
+ * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS
+ */
+ gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff);
gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
/* DS: data, read/write, 4 GB, base 0 */
gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
/* FS: data, read/write, 4 GB, base (Global Data Pointer) */
- id->arch.gd_addr = id;
+ new_gd->arch.gd_addr = new_gd;
gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
- (ulong)&id->arch.gd_addr, 0xfffff);
+ (ulong)&new_gd->arch.gd_addr, 0xfffff);
/* 16-bit CS: code, read/execute, 64 kB, base 0 */
gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
c->x86_model += ((tfms >> 16) & 0xF) << 4;
}
+u32 cpu_get_family_model(void)
+{
+ return gd->arch.x86_device & 0x0fff0ff0;
+}
+
+u32 cpu_get_stepping(void)
+{
+ return gd->arch.x86_mask;
+}
+
int x86_cpu_init_f(void)
{
const u32 em_rst = ~X86_CR0_EM;
}
}
+#ifdef CONFIG_I8254_TIMER
+ /* Set up the i8254 timer if required */
+ i8254_init();
+#endif
+
return 0;
}
__weak void reset_cpu(ulong addr)
{
/* Do a hard reset through the chipset's reset control register */
- outb(SYS_RST | RST_CPU, PORT_RESET);
+ outb(SYS_RST | RST_CPU, IO_PORT_RESET);
for (;;)
cpu_hlt();
}
void x86_full_reset(void)
{
- outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
+ outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
}
int dcache_status(void)
void show_boot_progress(int val)
{
-#if MIN_PORT80_KCLOCKS_DELAY
- /*
- * Scale the time counter reading to avoid using 64 bit arithmetics.
- * Can't use get_timer() here becuase it could be not yet
- * initialized or even implemented.
- */
- if (!gd->arch.tsc_prev) {
- gd->arch.tsc_base_kclocks = rdtsc() / 1000;
- gd->arch.tsc_prev = 0;
- } else {
- uint32_t now;
-
- do {
- now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
- } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
- gd->arch.tsc_prev = now;
- }
-#endif
outb(val, POST_PORT);
}
#ifndef CONFIG_SYS_COREBOOT
+/*
+ * Implement a weak default function for boards that optionally
+ * need to clean up the system before jumping to the kernel.
+ */
+__weak void board_final_cleanup(void)
+{
+}
+
int last_stage_init(void)
{
write_tables();
+ board_final_cleanup();
+
return 0;
}
#endif
}
#endif
-__weak int x86_init_cpus(void)
+static int x86_init_cpus(void)
{
#ifdef CONFIG_SMP
debug("Init additional CPUs\n");
int cpu_init_r(void)
{
- if (ll_boot_init())
- return x86_init_cpus();
+ struct udevice *dev;
+ int ret;
+
+ if (!ll_boot_init())
+ return 0;
+
+ ret = x86_init_cpus();
+ if (ret)
+ return ret;
+
+ /*
+ * Set up the northbridge, PCH and LPC if available. Note that these
+ * may have had some limited pre-relocation init if they were probed
+ * before relocation, but this is post relocation.
+ */
+ uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
+ uclass_first_device(UCLASS_PCH, &dev);
+ uclass_first_device(UCLASS_LPC, &dev);
return 0;
}
+
+#ifndef CONFIG_EFI_STUB
+int reserve_arch(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+ mrccache_reserve();
+#endif
+
+#ifdef CONFIG_SEABIOS
+ high_table_reserve();
+#endif
+
+ return 0;
+}
+#endif