#include <dm.h>
#include <errno.h>
#include <malloc.h>
+#include <syscon.h>
#include <asm/control_regs.h>
+#include <asm/coreboot_tables.h>
#include <asm/cpu.h>
#include <asm/lapic.h>
#include <asm/microcode.h>
struct gdt_ptr gdt;
gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
- gdt.ptr = (u32)boot_gdt;
+ gdt.ptr = (ulong)boot_gdt;
asm volatile("lgdtl %0\n" : : "m" (gdt));
}
memset(pgtable, '\0', PAGETABLE_SIZE);
/* Level 4 needs a single entry */
- pgtable[0] = (uint32_t)&pgtable[1024] + 7;
+ pgtable[0] = (ulong)&pgtable[1024] + 7;
/* Level 3 has one 64-bit entry for each GiB of memory */
- for (i = 0; i < 4; i++) {
- pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
- 0x1000 * i + 7;
- }
+ for (i = 0; i < 4; i++)
+ pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
for (i = 0; i < 2048; i++)
uclass_first_device(UCLASS_PCH, &dev);
uclass_first_device(UCLASS_LPC, &dev);
+ /* Set up pin control if available */
+ ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
+ debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
+
return 0;
}
int reserve_arch(void)
{
#ifdef CONFIG_ENABLE_MRC_CACHE
- return mrccache_reserve();
-#else
- return 0;
+ mrccache_reserve();
#endif
+
+#ifdef CONFIG_SEABIOS
+ high_table_reserve();
+#endif
+
+ return 0;
}
#endif