x86: Add some missing global_data declarations in files that use gd
[oweals/u-boot.git] / arch / x86 / cpu / coreboot / pci.c
index 7484c5c02a6770eb0bbe851149cc8a14c8f30d35..41e29a6086fdfb661ea521002c24f68426b119a2 100644 (file)
@@ -6,44 +6,20 @@
  * (C) Copyright 2002
  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
  *
- * SPDX-License-Identifier:    GPL-2.0+ 
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <dm.h>
 #include <pci.h>
-#include <asm/pci.h>
 
-static struct pci_controller coreboot_hose;
-
-static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
-                             struct pci_config_table *table)
-{
-       u8 secondary;
-       hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
-       hose->last_busno = max(hose->last_busno, secondary);
-       pci_hose_scan_bus(hose, secondary);
-}
-
-static struct pci_config_table pci_coreboot_config_table[] = {
-       /* vendor, device, class, bus, dev, func */
-       { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
-               PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
-       {}
+static const struct udevice_id generic_pch_ids[] = {
+       { .compatible = "intel,pch" },
+       { }
 };
 
-void pci_init_board(void)
-{
-       coreboot_hose.config_table = pci_coreboot_config_table;
-       coreboot_hose.first_busno = 0;
-       coreboot_hose.last_busno = 0;
-
-       pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
-               PCI_REGION_MEM);
-       coreboot_hose.region_count = 1;
-
-       pci_setup_type1(&coreboot_hose);
-
-       pci_register_hose(&coreboot_hose);
-
-       pci_hose_scan(&coreboot_hose);
-}
+U_BOOT_DRIVER(generic_pch_drv) = {
+       .name           = "pch",
+       .id             = UCLASS_PCH,
+       .of_match       = generic_pch_ids,
+};