Merge branch 'master' of git://git.denx.de/u-boot-atmel

[oweals/u-boot.git] / arch / x86 / Kconfig

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index fdfb6187b8e37c033198b7d63b851d29148aee48..90e828a26ee4b02290724868cceec5b6683a71b3 100644 (file)
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -32,19 +32,25 @@ config TARGET_CHROMEBOOK_LINK
          and it provides a 2560x1700 high resolution touch-enabled LCD
          display.
 
+config TARGET_CROWNBAY
+       bool "Support Intel Crown Bay CRB"
+       help
+         This is the Intel Crown Bay Customer Reference Board. It contains
+         the Intel Atom Processor E6xx populated on the COM Express module
+         with 1GB DDR2 soldered down memory and a carrier board with the
+         Intel Platform Controller Hub EG20T, other system components and
+         peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
+
 endchoice
 
 config RAMBASE
        hex
        default 0x100000
 
-config RAMTOP
-       hex
-       default 0x200000
-
 config XIP_ROM_SIZE
        hex
-       default 0x10000
+       depends on X86_RESET_VECTOR
+       default ROM_SIZE
 
 config CPU_ADDR_BITS
        int
@@ -61,6 +67,15 @@ config SMM_TSEG
 config SMM_TSEG_SIZE
        hex
 
+config X86_RESET_VECTOR
+       bool
+       default n
+
+config SYS_X86_START16
+       hex
+       depends on X86_RESET_VECTOR
+       default 0xfffff800
+
 config BOARD_ROMSIZE_KB_512
        bool
 config BOARD_ROMSIZE_KB_1024
@@ -76,6 +91,7 @@ config BOARD_ROMSIZE_KB_16384
 
 choice
        prompt "ROM chip size"
+       depends on X86_RESET_VECTOR
        default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
        default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
        default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
@@ -308,10 +324,36 @@ config FRAMEBUFFER_VESA_MODE
 
 endmenu
 
+config TSC_CALIBRATION_BYPASS
+       bool "Bypass Time-Stamp Counter (TSC) calibration"
+       default n
+       help
+         By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
+         running frequency via Model-Specific Register (MSR) and Programmable
+         Interval Timer (PIT). If the calibration does not work on your board,
+         select this option and provide a hardcoded TSC running frequency with
+         CONFIG_TSC_FREQ_IN_MHZ below.
+
+         Normally this option should be turned on in a simulation environment
+         like qemu.
+
+config TSC_FREQ_IN_MHZ
+       int "Time-Stamp Counter (TSC) running frequency in MHz"
+       depends on TSC_CALIBRATION_BYPASS
+       default 1000
+       help
+         The running frequency in MHz of Time-Stamp Counter (TSC).
+
+source "arch/x86/cpu/coreboot/Kconfig"
+
 source "arch/x86/cpu/ivybridge/Kconfig"
 
+source "arch/x86/cpu/queensbay/Kconfig"
+
 source "board/coreboot/coreboot/Kconfig"
 
 source "board/google/chromebook_link/Kconfig"
 
+source "board/intel/crownbay/Kconfig"
+
 endmenu