Merge tag 'mips-fixes-for-2019.07' of https://gitlab.denx.de/u-boot/custodians/u...

[oweals/u-boot.git] / arch / sandbox / dts / sandbox_pmic.dtsi

diff --git a/arch/sandbox/dts/sandbox_pmic.dtsi b/arch/sandbox/dts/sandbox_pmic.dtsi
index acb479939645913f6df90f59a70e5cd8097176b8..565c382ed45c2d83a1b423074eec069ed1ca25e6 100644 (file)
--- a/arch/sandbox/dts/sandbox_pmic.dtsi
+++ b/arch/sandbox/dts/sandbox_pmic.dtsi
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  *  Sandbox PMIC dts node
  *
  *  Copyright (C) 2015 Samsung Electronics
  *  Przemyslaw Marczak  <p.marczak@samsung.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <dt-bindings/pmic/sandbox_pmic.h>
@@ -12,40 +11,6 @@
 &sandbox_pmic {
        compatible = "sandbox,pmic";
 
-       pmic_emul {
-               compatible = "sandbox,i2c-pmic";
-
-               /*
-                * Default PMICs register values are set by macro
-                * VAL2REG(min, step, value) [uV/uA]
-                * VAL2OMREG(mode id)
-                * reg-defaults - byte array
-                */
-               reg-defaults = /bits/ 8 <
-                       /* BUCK1 */
-                       VAL2REG(800000, 25000, 1000000)
-                       VAL2REG(150000, 25000, 150000)
-                       VAL2OMREG(BUCK_OM_OFF)
-                       /* BUCK2 */
-                       VAL2REG(750000, 50000, 3000000)
-                       VAL2REG(150000, 25000, 150000)
-                       VAL2OMREG(0)
-                       /* LDO1 */
-                       VAL2REG(800000, 25000, 1600000)
-                       VAL2REG(100000, 50000, 150000)
-                       VAL2OMREG(LDO_OM_OFF)
-                       /* LDO2 */
-                       VAL2REG(750000, 50000, 3000000)
-                       VAL2REG(150000, 25000, 150000)
-                       VAL2OMREG(0)
-                       /* reg[12:15] - not used */
-                       0x00
-                       0x00
-                       0x00
-                       0x00
-               >;
-       };
-
        buck1 {
                regulator-name = "SUPPLY_1.2V";
                regulator-min-microvolt = <1200000>;
@@ -61,7 +26,7 @@
                regulator-max-microvolt = <3300000>;
        };
 
-       ldo1 {
+       ldo_1: ldo1 {
                regulator-name = "VDD_EMMC_1.8V";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <1800000>;
@@ -82,3 +47,71 @@
                regulator-max-microvolt = <1500000>;
        };
 };
+
+&mc34708 {
+       compatible = "fsl,mc34708";
+};
+
+&i2c_emul {
+       emul_pmic0: pmic-emul0 {
+               compatible = "sandbox,i2c-pmic";
+
+               /*
+                * Default PMICs register values are set by macro
+                * VAL2REG(min, step, value) [uV/uA]
+                * VAL2OMREG(mode id)
+                * reg-defaults - byte array
+                */
+               reg-defaults = /bits/ 8 <
+                       /* BUCK1 */
+                       VAL2REG(800000, 25000, 1000000)
+                       VAL2REG(150000, 25000, 150000)
+                       VAL2OMREG(BUCK_OM_OFF)
+                       /* BUCK2 */
+                       VAL2REG(750000, 50000, 3000000)
+                       VAL2REG(150000, 25000, 150000)
+                       VAL2OMREG(0)
+                       /* LDO1 */
+                       VAL2REG(800000, 25000, 1600000)
+                       VAL2REG(100000, 50000, 150000)
+                       VAL2OMREG(LDO_OM_OFF)
+                       /* LDO2 */
+                       VAL2REG(750000, 50000, 3000000)
+                       VAL2REG(150000, 25000, 150000)
+                       VAL2OMREG(0)
+                       /* reg[12:15] - not used */
+                       0x00
+                       0x00
+                       0x00
+                       0x00
+               >;
+       };
+
+       emul_pmic1: pmic-emul1 {
+               compatible = "sandbox,i2c-pmic";
+               reg-defaults = /bits/ 8 <
+                       0x00 0x80 0x08 0xff 0xff 0xff 0x2e 0x01 0x08
+                       0x40 0x80 0x81 0x5f 0xff 0xfb 0x1e 0x80 0x18
+                       0x00 0x00 0x0e 0x00 0x00 0x14 0x00 0x00 0x00
+                       0x00 0x00 0x20 0x00 0x01 0x3a 0x00 0x00 0x00
+                       0x00 0x00 0x00 0x00 0x00 0x40 0x00 0x00 0x00
+                       0x42 0x21 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+                       0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x5f
+                       0x01 0xff 0xff 0x00 0x00 0x00 0x00 0x7f 0xff
+                       0x92 0x49 0x24 0x59 0x6d 0x34 0x18 0xc1 0x8c
+                       0x00 0x60 0x18 0x51 0x48 0x45 0x14 0x51 0x45
+                       0x00 0x06 0x32 0x00 0x00 0x00 0x06 0x9c 0x99
+                       0x00 0x38 0x0a 0x00 0x38 0x0a 0x00 0x38 0x0a
+                       0x00 0x38 0x0a 0x84 0x00 0x00 0x00 0x00 0x00
+                       0x80 0x90 0x8f 0xf8 0x00 0x04 0x00 0x00 0x00
+                       0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+                       0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+                       0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+                       0x01 0x31 0x7e 0x2b 0x03 0xfd 0xc0 0x36 0x1b
+                       0x60 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+                       0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+                       0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+                       0x00 0x00 0x00
+               >;
+       };
+};