Merge branch 'master' of git://git.denx.de/u-boot-samsung

[oweals/u-boot.git] / arch / riscv / cpu / start.S

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 9804a8ac44107b4993fbe2c78d6590f28041d8a8..81ea52b170f7f898e56b32c2ace08a602609ecf8 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -14,6 +14,7 @@
 #include <common.h>
 #include <elf.h>
 #include <asm/encoding.h>
+#include <generated/asm-offsets.h>
 
 #ifdef CONFIG_32BIT
 #define LREG                   lw
@@ -34,21 +35,19 @@
 .section .text
 .globl _start
 _start:
-       j       handle_reset
+       /* save hart id and dtb pointer */
+       mv      s0, a0
+       mv      s1, a1
 
-nmi_vector:
-       j       nmi_vector
+       la      t0, trap_entry
+       csrw    MODE_PREFIX(tvec), t0
 
-trap_vector:
-       j       trap_entry
+       /* mask all interrupts */
+       csrw    MODE_PREFIX(ie), zero
 
-handle_reset:
-       li      t0, CONFIG_SYS_SDRAM_BASE
-       SREG    a2, 0(t0)
-       la      t0, trap_entry
-       csrw    mtvec, t0
-       csrwi   mstatus, 0
-       csrwi   mie, 0
+       /* Enable cache */
+       jal     icache_enable
+       jal     dcache_enable
 
 /*
  * Set stackpointer in internal/ex RAM to call board_init_f
@@ -66,8 +65,15 @@ call_board_init_f_0:
        mv      a0, sp
        jal     board_init_f_alloc_reserve
        mv      sp, a0
+
+       la      t0, prior_stage_fdt_address
+       SREG    s1, 0(t0)
+
        jal     board_init_f_init_reserve
 
+       /* save the boot hart id to global_data */
+       SREG    s0, GD_BOOT_HART(gp)
+
        mv      a0, zero                /* a0 <-- boot_flags = 0 */
        la      t5, board_init_f
        jr      t5                      /* jump to board_init_f() */
@@ -148,8 +154,8 @@ fix_rela_dyn:
        LREG    t3, -(REGBYTES*3)(t1)
        li      t5, SYM_SIZE
        mul     t0, t0, t5
-       add     s1, t4, t0
-       LREG    t5, REGBYTES(s1)
+       add     s5, t4, t0
+       LREG    t5, REGBYTES(s5)
        add     t5, t5, t6              /* t5 <-- location to fix up in RAM */
        add     t3, t3, t6              /* t3 <-- location to fix up in RAM */
        SREG    t5, 0(t3)
@@ -162,18 +168,17 @@ fix_rela_dyn:
 */
        la      t0, trap_entry
        add     t0, t0, t6
-       csrw    mtvec, t0
+       csrw    MODE_PREFIX(tvec), t0
 
 clear_bss:
        la      t0, __bss_start         /* t0 <- rel __bss_start in FLASH */
        add     t0, t0, t6              /* t0 <- rel __bss_start in RAM */
        la      t1, __bss_end           /* t1 <- rel __bss_end in FLASH */
        add     t1, t1, t6              /* t1 <- rel __bss_end in RAM */
-       li      t2, 0x00000000          /* clear */
        beq     t0, t1, call_board_init_r
 
 clbss_l:
-       SREG    t2, 0(t0)               /* clear loop... */
+       SREG    zero, 0(t0)             /* clear loop... */
        addi    t0, t0, REGBYTES
        bne     t0, t1, clbss_l
 
@@ -182,6 +187,8 @@ clbss_l:
  * initialization, now running from RAM.
  */
 call_board_init_r:
+       jal     invalidate_icache_all
+       jal     flush_dcache_all
        la      t0, board_init_r
        mv      t4, t0                  /* offset of board_init_r() */
        add     t4, t4, t6              /* real address of board_init_r() */
@@ -195,85 +202,3 @@ call_board_init_r:
  * jump to it ...
  */
        jr      t4                      /* jump to board_init_r() */
-
-/*
- * trap entry
- */
-.align 2
-trap_entry:
-       addi    sp, sp, -32*REGBYTES
-       SREG    x1, 1*REGBYTES(sp)
-       SREG    x2, 2*REGBYTES(sp)
-       SREG    x3, 3*REGBYTES(sp)
-       SREG    x4, 4*REGBYTES(sp)
-       SREG    x5, 5*REGBYTES(sp)
-       SREG    x6, 6*REGBYTES(sp)
-       SREG    x7, 7*REGBYTES(sp)
-       SREG    x8, 8*REGBYTES(sp)
-       SREG    x9, 9*REGBYTES(sp)
-       SREG    x10, 10*REGBYTES(sp)
-       SREG    x11, 11*REGBYTES(sp)
-       SREG    x12, 12*REGBYTES(sp)
-       SREG    x13, 13*REGBYTES(sp)
-       SREG    x14, 14*REGBYTES(sp)
-       SREG    x15, 15*REGBYTES(sp)
-       SREG    x16, 16*REGBYTES(sp)
-       SREG    x17, 17*REGBYTES(sp)
-       SREG    x18, 18*REGBYTES(sp)
-       SREG    x19, 19*REGBYTES(sp)
-       SREG    x20, 20*REGBYTES(sp)
-       SREG    x21, 21*REGBYTES(sp)
-       SREG    x22, 22*REGBYTES(sp)
-       SREG    x23, 23*REGBYTES(sp)
-       SREG    x24, 24*REGBYTES(sp)
-       SREG    x25, 25*REGBYTES(sp)
-       SREG    x26, 26*REGBYTES(sp)
-       SREG    x27, 27*REGBYTES(sp)
-       SREG    x28, 28*REGBYTES(sp)
-       SREG    x29, 29*REGBYTES(sp)
-       SREG    x30, 30*REGBYTES(sp)
-       SREG    x31, 31*REGBYTES(sp)
-       csrr    a0, mcause
-       csrr    a1, mepc
-       mv      a2, sp
-       jal     handle_trap
-       csrw    mepc, a0
-
-/*
- * Remain in M-mode after mret
- */
-       li      t0, MSTATUS_MPP
-       csrs    mstatus, t0
-       LREG    x1, 1*REGBYTES(sp)
-       LREG    x2, 2*REGBYTES(sp)
-       LREG    x3, 3*REGBYTES(sp)
-       LREG    x4, 4*REGBYTES(sp)
-       LREG    x5, 5*REGBYTES(sp)
-       LREG    x6, 6*REGBYTES(sp)
-       LREG    x7, 7*REGBYTES(sp)
-       LREG    x8, 8*REGBYTES(sp)
-       LREG    x9, 9*REGBYTES(sp)
-       LREG    x10, 10*REGBYTES(sp)
-       LREG    x11, 11*REGBYTES(sp)
-       LREG    x12, 12*REGBYTES(sp)
-       LREG    x13, 13*REGBYTES(sp)
-       LREG    x14, 14*REGBYTES(sp)
-       LREG    x15, 15*REGBYTES(sp)
-       LREG    x16, 16*REGBYTES(sp)
-       LREG    x17, 17*REGBYTES(sp)
-       LREG    x18, 18*REGBYTES(sp)
-       LREG    x19, 19*REGBYTES(sp)
-       LREG    x20, 20*REGBYTES(sp)
-       LREG    x21, 21*REGBYTES(sp)
-       LREG    x22, 22*REGBYTES(sp)
-       LREG    x23, 23*REGBYTES(sp)
-       LREG    x24, 24*REGBYTES(sp)
-       LREG    x25, 25*REGBYTES(sp)
-       LREG    x26, 26*REGBYTES(sp)
-       LREG    x27, 27*REGBYTES(sp)
-       LREG    x28, 28*REGBYTES(sp)
-       LREG    x29, 29*REGBYTES(sp)
-       LREG    x30, 30*REGBYTES(sp)
-       LREG    x31, 31*REGBYTES(sp)
-       addi    sp, sp, 32*REGBYTES
-       mret