riscv: Add SiFive FU540 board support

[oweals/u-boot.git] / arch / riscv / Kconfig

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 20a43d88e37b31d9ae7d71ecfe6755cc3aa99f1f..36512a8995005062b48e538bbae5db553a613f0a 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -1,4 +1,4 @@
-menu "RISCV architecture"
+menu "RISC-V architecture"
        depends on RISCV
 
 config SYS_ARCH
@@ -11,32 +11,113 @@ choice
 config TARGET_AX25_AE350
        bool "Support ax25-ae350"
 
+config TARGET_QEMU_VIRT
+       bool "Support QEMU Virt Board"
+
+config TARGET_SIFIVE_FU540
+       bool "Support SiFive FU540 Board"
+
 endchoice
 
+# board-specific options below
 source "board/AndesTech/ax25-ae350/Kconfig"
+source "board/emulation/qemu-riscv/Kconfig"
+source "board/sifive/fu540/Kconfig"
+
+# platform-specific options below
+source "arch/riscv/cpu/ax25/Kconfig"
+source "arch/riscv/cpu/generic/Kconfig"
+
+# architecture-specific options below
 
 choice
-       prompt "CPU selection"
-       default CPU_RISCV_32
+       prompt "Base ISA"
+       default ARCH_RV32I
 
-config CPU_RISCV_32
-       bool "RISCV 32 bit"
+config ARCH_RV32I
+       bool "RV32I"
        select 32BIT
        help
-         Choose this option to build an U-Boot for RISCV32 architecture.
+         Choose this option to target the RV32I base integer instruction set.
 
-config CPU_RISCV_64
-       bool "RISCV 64 bit"
+config ARCH_RV64I
+       bool "RV64I"
        select 64BIT
+       select PHYS_64BIT
+       help
+         Choose this option to target the RV64I base integer instruction set.
+
+endchoice
+
+choice
+       prompt "Code Model"
+       default CMODEL_MEDLOW
+
+config CMODEL_MEDLOW
+       bool "medium low code model"
+       help
+         U-Boot and its statically defined symbols must lie within a single 2 GiB
+         address range and must lie between absolute addresses -2 GiB and +2 GiB.
+
+config CMODEL_MEDANY
+       bool "medium any code model"
+       help
+         U-Boot and its statically defined symbols must be within any single 2 GiB
+         address range.
+
+endchoice
+
+choice
+       prompt "Run Mode"
+       default RISCV_MMODE
+
+config RISCV_MMODE
+       bool "Machine"
+       help
+         Choose this option to build U-Boot for RISC-V M-Mode.
+
+config RISCV_SMODE
+       bool "Supervisor"
        help
-         Choose this option to build an U-Boot for RISCV64 architecture.
+         Choose this option to build U-Boot for RISC-V S-Mode.
 
 endchoice
 
+config RISCV_ISA_C
+       bool "Emit compressed instructions"
+       default y
+       help
+         Adds "C" to the ISA subsets that the toolchain is allowed to emit
+         when building U-Boot, which results in compressed instructions in the
+         U-Boot binary.
+
+config RISCV_ISA_A
+       def_bool y
+
 config 32BIT
        bool
 
 config 64BIT
        bool
 
+config SIFIVE_CLINT
+       bool
+       depends on RISCV_MMODE
+       select REGMAP
+       select SYSCON
+       help
+         The SiFive CLINT block holds memory-mapped control and status registers
+         associated with software and timer interrupts.
+
+config RISCV_RDTIME
+       bool
+       default y if RISCV_SMODE
+       help
+         The provides the riscv_get_time() API that is implemented using the
+         standard rdtime instruction. This is the case for S-mode U-Boot, and
+         is useful for processors that support rdtime in M-mode too.
+
+config SYS_MALLOC_F_LEN
+       default 0x1000
+
 endmenu