sh: sh2: Remove CPU support

[oweals/u-boot.git] / arch / riscv / Kconfig

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3a4470daf3f33791a41804def025e170594c190d..362f3cdc6558bb1c51ca839225ccafbabcc6d0b5 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -109,6 +109,24 @@ config SIFIVE_CLINT
          The SiFive CLINT block holds memory-mapped control and status registers
          associated with software and timer interrupts.
 
+config ANDES_PLIC
+       bool
+       depends on RISCV_MMODE
+       select REGMAP
+       select SYSCON
+       help
+         The Andes PLIC block holds memory-mapped claim and pending registers
+         associated with software interrupt.
+
+config ANDES_PLMT
+       bool
+       depends on RISCV_MMODE
+       select REGMAP
+       select SYSCON
+       help
+         The Andes PLMT block holds memory-mapped mtime register
+         associated with timer tick.
+
 config RISCV_RDTIME
        bool
        default y if RISCV_SMODE
@@ -144,6 +162,13 @@ config SBI_IPI
        default y if RISCV_SMODE
        depends on SMP
 
+config XIP
+       bool "XIP mode"
+       help
+         XIP (eXecute In Place) is a method for executing code directly
+         from a NOR flash memory without copying the code to ram.
+         Say yes here if U-Boot boots from flash directly.
+
 config STACK_SIZE_SHIFT
        int
        default 13