Merge branch 'master' of git://git.denx.de/u-boot-sh

[oweals/u-boot.git] / arch / riscv / Kconfig

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ae8ff7b765786841971eedfa06cb4257418e375d..01975d7c60c4171dabc8fa1bc437f5789fddab48 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -11,6 +11,9 @@ choice
 config TARGET_AX25_AE350
        bool "Support ax25-ae350"
 
+config TARGET_MICROCHIP_ICICLE
+       bool "Support Microchip PolarFire-SoC Icicle Board"
+
 config TARGET_QEMU_VIRT
        bool "Support QEMU Virt Board"
 
@@ -19,9 +22,36 @@ config TARGET_SIFIVE_FU540
 
 endchoice
 
+config SYS_ICACHE_OFF
+       bool "Do not enable icache"
+       default n
+       help
+         Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+       bool "Do not enable icache in SPL"
+       depends on SPL
+       default SYS_ICACHE_OFF
+       help
+         Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+       bool "Do not enable dcache"
+       default n
+       help
+         Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+       bool "Do not enable dcache in SPL"
+       depends on SPL
+       default SYS_DCACHE_OFF
+       help
+         Do not enable data cache in SPL.
+
 # board-specific options below
 source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
+source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/fu540/Kconfig"
 
 # platform-specific options below
@@ -83,6 +113,23 @@ config RISCV_SMODE
 
 endchoice
 
+choice
+       prompt "SPL Run Mode"
+       default SPL_RISCV_MMODE
+       depends on SPL
+
+config SPL_RISCV_MMODE
+       bool "Machine"
+       help
+         Choose this option to build U-Boot SPL for RISC-V M-Mode.
+
+config SPL_RISCV_SMODE
+       bool "Supervisor"
+       help
+         Choose this option to build U-Boot SPL for RISC-V S-Mode.
+
+endchoice
+
 config RISCV_ISA_C
        bool "Emit compressed instructions"
        default y
@@ -102,34 +149,40 @@ config 64BIT
 
 config SIFIVE_CLINT
        bool
-       depends on RISCV_MMODE
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
        select REGMAP
        select SYSCON
+       select SPL_REGMAP if SPL
+       select SPL_SYSCON if SPL
        help
          The SiFive CLINT block holds memory-mapped control and status registers
          associated with software and timer interrupts.
 
 config ANDES_PLIC
        bool
-       depends on RISCV_MMODE
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
        select REGMAP
        select SYSCON
+       select SPL_REGMAP if SPL
+       select SPL_SYSCON if SPL
        help
          The Andes PLIC block holds memory-mapped claim and pending registers
          associated with software interrupt.
 
 config ANDES_PLMT
        bool
-       depends on RISCV_MMODE
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
        select REGMAP
        select SYSCON
+       select SPL_REGMAP if SPL
+       select SPL_SYSCON if SPL
        help
          The Andes PLMT block holds memory-mapped mtime register
          associated with timer tick.
 
 config RISCV_RDTIME
        bool
-       default y if RISCV_SMODE
+       default y if RISCV_SMODE || SPL_RISCV_SMODE
        help
          The provides the riscv_get_time() API that is implemented using the
          standard rdtime instruction. This is the case for S-mode U-Boot, and
@@ -159,11 +212,21 @@ config NR_CPUS
 
 config SBI_IPI
        bool
-       default y if RISCV_SMODE
+       default y if RISCV_SMODE || SPL_RISCV_SMODE
        depends on SMP
 
+config XIP
+       bool "XIP mode"
+       help
+         XIP (eXecute In Place) is a method for executing code directly
+         from a NOR flash memory without copying the code to ram.
+         Say yes here if U-Boot boots from flash directly.
+
 config STACK_SIZE_SHIFT
        int
        default 13
 
+config SPL_LDSCRIPT
+       default "arch/riscv/cpu/u-boot-spl.lds"
+
 endmenu