#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
+#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
+#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
+
+/* e6500 */
+#define L2CSR0_L2REP_SPLRUAGE 0x00000000 /* L2REP Streaming PLRU with Aging */
+#define L2CSR0_L2REP_FIFO 0x00001000 /* L2REP FIFO */
+#define L2CSR0_L2REP_SPLRU 0x00002000 /* L2REP Streaming PLRU */
+#define L2CSR0_L2REP_PLRU 0x00003000 /* L2REP PLRU */
+
+#define L2CSR0_L2REP_MODE L2CSR0_L2REP_SPLRUAGE
+
#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
+#define TLBnCFG_NENTRY_MASK 0x00000fff
#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */
#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
#define SPRN_MSSSR0 0x3f7
#endif
+#define SPRN_HDBCR0 0x3d0
+#define SPRN_HDBCR1 0x3d1
+#define SPRN_HDBCR2 0x3d2
+#define SPRN_HDBCR3 0x3d3
+#define SPRN_HDBCR4 0x3d4
+#define SPRN_HDBCR5 0x3d5
+#define SPRN_HDBCR6 0x3d6
+#define SPRN_HDBCR7 0x277
+#define SPRN_HDBCR8 0x278
+
/* Short-hand versions for a number of the above SPRNs */
#define CTR SPRN_CTR /* Counter Register */
/* System-On-Chip Version Register (SVR) field extraction */
#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
-#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
+#define SVR_REV(svr) (((svr) >> 0) & 0xFF) /* Revision field */
#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
#define PVR_405GP_RC 0x40110082
#define PVR_405GP_RD 0x401100C4
#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
-#define PVR_405CR_RA 0x40110041
-#define PVR_405CR_RB 0x401100C5
-#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
#define PVR_405EP_RA 0x51210950
#define PVR_405GPR_RB 0x50910951
#define PVR_405EZ_RA 0x41511460
#define PVR_VER_E500_V2 0x8021
#define PVR_VER_E500MC 0x8023
#define PVR_VER_E5500 0x8024
+#define PVR_VER_E6500 0x8040
#define PVR_86xx 0x80040000
/* System Version Register (SVR) field extraction */
-#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
-#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */
-
#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */
#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
#define SVR_P1012 0x80E501
#define SVR_P1013 0x80E700
#define SVR_P1014 0x80F101
-#define SVR_P1015 0x80E502
-#define SVR_P1016 0x80E503
#define SVR_P1017 0x80F700
#define SVR_P1020 0x80E400
#define SVR_P1021 0x80E401
#define SVR_P2040 0x821000
#define SVR_P2041 0x821001
#define SVR_P3041 0x821103
-#define SVR_P3060 0x820002
#define SVR_P4040 0x820100
#define SVR_P4080 0x820000
#define SVR_P5010 0x822100
#define SVR_P5020 0x822000
+#define SVR_P5021 0X820500
+#define SVR_P5040 0x820400
+#define SVR_T4240 0x824000
+#define SVR_T4120 0x824001
+#define SVR_T4160 0x824100
+#define SVR_C291 0x850000
+#define SVR_C292 0x850020
+#define SVR_C293 0x850030
+#define SVR_B4860 0X868000
+#define SVR_G4860 0x868001
+#define SVR_G4060 0x868003
+#define SVR_B4440 0x868100
+#define SVR_G4440 0x868101
+#define SVR_B4420 0x868102
+#define SVR_B4220 0x868103
+#define SVR_T1040 0x852000
+#define SVR_T1041 0x852001
+#define SVR_T1042 0x852002
+#define SVR_T1020 0x852100
+#define SVR_T1021 0x852101
+#define SVR_T1022 0x852102
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
#define SVR_8641D 0x809001
#define SVR_9130 0x860001
-#define SVR_9130_E 0x860801
#define SVR_9131 0x860000
-#define SVR_9131_E 0x860800
+#define SVR_9132 0x861000
+#define SVR_9232 0x861400
#define SVR_Unknown 0xFFFFFF
};
struct cpu_type *identify_cpu(u32 ver);
+int fixup_cpu(void);
+
+int fsl_qoriq_core_to_cluster(unsigned int core);
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
#define CPU_TYPE_ENTRY(n, v, nc) \
#endif
#endif /* CONFIG_MACH_SPECIFIC */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_440)
+ #define EPAPR_MAGIC (0x45504150)
+#else
+ #define EPAPR_MAGIC (0x65504150)
+#endif
+
#endif /* __ASM_PPC_PROCESSOR_H */
projects / oweals / u-boot.git / blobdiff