secure_boot: enable chain of trust for PowerPC platforms

[oweals/u-boot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index f89b90b724ae7a739ab39a6537daed024f7cba25..fd8aba42a55017df455604541e2a38023cd6c8b6 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -19,7 +19,7 @@
 #include <fsl_sec.h>
 #include <fsl_sfp.h>
 #include <asm/fsl_lbc.h>
-#include <asm/fsl_fman.h>
+#include <fsl_fman.h>
 #include <fsl_immap.h>
 
 typedef struct ccsr_local {
@@ -1749,6 +1749,8 @@ typedef struct ccsr_gur {
        u32     brrl;           /* Boot release */
        u8      res17[24];
        u32     rcwsr[16];      /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX    7
+#define RCW_SB_EN_MASK         0x00200000
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT   16
@@ -2194,6 +2196,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR2_DDR_SPD_0    0x00000008
 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT      3
 #endif
+#define MPC85xx_PORDEVSR2_SBC_MASK     0x10000000
 /* The 8544 RM says this is bit 26, but it's really bit 24 */
 #define MPC85xx_PORDEVSR2_SEC_CFG      0x00000080
        u8      res1[8];
@@ -2883,6 +2886,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET                0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET              0x300000
 #define CONFIG_SYS_FSL_JR0_OFFSET              0x301000
+#define CONFIG_SYS_SEC_MON_OFFSET              0x314000
 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET      0x316000
 #define CONFIG_SYS_FSL_QMAN_OFFSET             0x318000
 #define CONFIG_SYS_FSL_BMAN_OFFSET             0x31a000
@@ -2950,7 +2954,7 @@ struct ccsr_pman {
 #endif
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET      0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET      0xE3000
-#define CONFIG_SYS_SNVS_OFFSET                 0xE6000
+#define CONFIG_SYS_SEC_MON_OFFSET              0xE6000
 #define CONFIG_SYS_SFP_OFFSET                  0xE7000
 #define CONFIG_SYS_MPC85xx_CPM_OFFSET          0x80000
 #define CONFIG_SYS_FSL_QMAN_OFFSET             0x88000
@@ -3080,6 +3084,9 @@ struct ccsr_pman {
 #define CONFIG_SYS_SFP_ADDR  \
        (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
 
+#define CONFIG_SYS_SEC_MON_ADDR  \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
+
 #define TSEC_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)