Merge branch 'master' of git://git.denx.de/u-boot-samsung

[oweals/u-boot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 361be6f45dfe95c70cebcc4f00d362a902588749..c045a24d1aba15471434c22abfc6cae2fb56f66a 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -17,8 +17,9 @@
 #include <asm/fsl_i2c.h>
 #include <fsl_ifc.h>
 #include <fsl_sec.h>
+#include <fsl_sfp.h>
 #include <asm/fsl_lbc.h>
-#include <asm/fsl_fman.h>
+#include <fsl_fman.h>
 #include <fsl_immap.h>
 
 typedef struct ccsr_local {
@@ -119,8 +120,8 @@ typedef struct ccsr_local_ecm {
 
 /* I2C Registers */
 typedef struct ccsr_i2c {
-       struct fsl_i2c  i2c[1];
-       u8      res[4096 - 1 * sizeof(struct fsl_i2c)];
+       struct fsl_i2c_base     i2c[1];
+       u8      res[4096 - 1 * sizeof(struct fsl_i2c_base)];
 } ccsr_i2c_t;
 
 #if defined(CONFIG_MPC8540) \
@@ -264,6 +265,7 @@ typedef struct ccsr_pcix {
 #define PIWAR_WRITE_SNOOP      0x00005000
 #define PIWAR_MEM_2G           0x0000001e
 
+#ifndef CONFIG_MPC85XX_GPIO
 typedef struct ccsr_gpio {
        u32     gpdir;
        u32     gpodr;
@@ -272,6 +274,7 @@ typedef struct ccsr_gpio {
        u32     gpimr;
        u32     gpicr;
 } ccsr_gpio_t;
+#endif
 
 /* L2 Cache Registers */
 typedef struct ccsr_l2cache {
@@ -1748,6 +1751,8 @@ typedef struct ccsr_gur {
        u32     brrl;           /* Boot release */
        u8      res17[24];
        u32     rcwsr[16];      /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX    7
+#define RCW_SB_EN_MASK         0x00200000
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT   16
@@ -1803,6 +1808,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET_RCWSR13_EC2                        0x0c000000
 #define FSL_CORENET_RCWSR13_EC2_RGMII          0x08000000
 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET    0x28
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET    0xd00
 #define PXCKEN_MASK                            0x80000000
 #define PXCK_MASK                              0x00FF0000
 #define PXCK_BITS_START                                16
@@ -1931,7 +1937,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
        u8      res24[64];
        u32     pblsr;          /* Preboot loader status */
        u32     pamubypenr;     /* PAMU bypass enable */
-#define FSL_CORENET_PAMU_BYPASS                0xffff0000
        u32     dmacr1;         /* DMA control */
        u8      res25[4];
        u32     gensr1;         /* General status */
@@ -2192,6 +2197,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR2_DDR_SPD_0    0x00000008
 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT      3
 #endif
+#define MPC85xx_PORDEVSR2_SBC_MASK     0x10000000
 /* The 8544 RM says this is bit 26, but it's really bit 24 */
 #define MPC85xx_PORDEVSR2_SEC_CFG      0x00000080
        u8      res1[8];
@@ -2769,6 +2775,21 @@ typedef struct ccsr_pme {
        u8      res4[0x400];
 } ccsr_pme_t;
 
+struct ccsr_pamu {
+       u32 ppbah;
+       u32 ppbal;
+       u32 pplah;
+       u32 pplal;
+       u32 spbah;
+       u32 spbal;
+       u32 splah;
+       u32 splal;
+       u32 obah;
+       u32 obal;
+       u32 olah;
+       u32 olal;
+};
+
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 struct ccsr_raide {
        u8      res0[0x543];
@@ -2822,21 +2843,6 @@ struct ccsr_pman {
        u8      res_f4[0xf0c];
 };
 #endif
-#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
-struct ccsr_sfp_regs {
-       u32 ospr;               /* 0x200 */
-       u32 reserved0[14];
-       u32 srk_hash[8];        /* 0x23c Super Root Key Hash */
-       u32 oem_uid;            /* 0x9c OEM Unique ID */
-       u8 reserved2[0x04];
-       u32 ovpr;                       /* 0xA4  Intent To Secure */
-       u8 reserved4[0x08];
-       u32 fsl_uid;            /* 0xB0  FSL Unique ID */
-       u8 reserved5[0x04];
-       u32 fsl_spfr0;          /* Scratch Pad Fuse Register 0 */
-       u32 fsl_spfr1;          /* Scratch Pad Fuse Register 1 */
-};
-#endif
 
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET      0x0000
@@ -2864,6 +2870,7 @@ struct ccsr_sfp_regs {
 #define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET  0xED000
 #define CONFIG_SYS_FSL_CPC_OFFSET              0x10000
 #define CONFIG_SYS_FSL_SCFG_OFFSET             0xFC000
+#define CONFIG_SYS_FSL_PAMU_OFFSET             0x20000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET         0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET         0x101000
 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET         0x102000
@@ -2896,6 +2903,7 @@ struct ccsr_sfp_regs {
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET                0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET              0x300000
 #define CONFIG_SYS_FSL_JR0_OFFSET              0x301000
+#define CONFIG_SYS_SEC_MON_OFFSET              0x314000
 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET      0x316000
 #define CONFIG_SYS_FSL_QMAN_OFFSET             0x318000
 #define CONFIG_SYS_FSL_BMAN_OFFSET             0x31a000
@@ -2963,7 +2971,7 @@ struct ccsr_sfp_regs {
 #endif
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET      0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET      0xE3000
-#define CONFIG_SYS_SNVS_OFFSET                 0xE6000
+#define CONFIG_SYS_SEC_MON_OFFSET              0xE6000
 #define CONFIG_SYS_SFP_OFFSET                  0xE7000
 #define CONFIG_SYS_MPC85xx_CPM_OFFSET          0x80000
 #define CONFIG_SYS_FSL_QMAN_OFFSET             0x88000
@@ -2990,6 +2998,8 @@ struct ccsr_sfp_regs {
        (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
 #define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR        \
        (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
+       (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
 #define CONFIG_SYS_FSL_QMAN_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
 #define CONFIG_SYS_FSL_BMAN_ADDR \
@@ -3074,6 +3084,8 @@ struct ccsr_sfp_regs {
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
 #define CONFIG_SYS_FSL_SRIO_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
+#define CONFIG_SYS_PAMU_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
 
 #define CONFIG_SYS_PCI1_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
@@ -3091,6 +3103,9 @@ struct ccsr_sfp_regs {
 #define CONFIG_SYS_SFP_ADDR  \
        (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
 
+#define CONFIG_SYS_SEC_MON_ADDR  \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
+
 #define TSEC_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)