+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* MPC85xx Internal Memory Map
*
*
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMMAP_85xx__
#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
#define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
-#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
-#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x04000000
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
-#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080
#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000