Merge git://git.denx.de/u-boot-sunxi

[oweals/u-boot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 762b174b2d64213602f3e2e3d214dce0fbc93928..7995093621040835b1522a1d8652517eedecfbbc 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * MPC85xx Internal Memory Map
  *
@@ -5,8 +6,6 @@
  *
  * Copyright(c) 2002,2003 Motorola Inc.
  * Xianghua Xiao (x.xiao@motorola.com)
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __IMMAP_85xx__
@@ -2523,7 +2522,11 @@ typedef struct ccsr_gur {
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define MAX_SERDES 4
+#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#define SRDS_MAX_LANES 4
+#else
 #define SRDS_MAX_LANES 8
+#endif
 #define SRDS_MAX_BANK 2
 typedef struct serdes_corenet {
        struct {
@@ -2698,66 +2701,6 @@ enum {
        FSL_SRDS_B3_LANE_D = 23,
 };
 
-typedef struct ccsr_qman {
-#ifdef CONFIG_SYS_FSL_QMAN_V3
-       u8      res0[0x200];
-#else
-       struct {
-               u32     qcsp_lio_cfg;   /* 0x0 - SW Portal n LIO cfg */
-               u32     qcsp_io_cfg;    /* 0x4 - SW Portal n IO cfg */
-               u32     res;
-               u32     qcsp_dd_cfg;    /* 0xc - SW Portal n Dynamic Debug cfg */
-       } qcsp[32];
-#endif
-       /* Not actually reserved, but irrelevant to u-boot */
-       u8      res[0xbf8 - 0x200];
-       u32     ip_rev_1;
-       u32     ip_rev_2;
-       u32     fqd_bare;       /* FQD Extended Base Addr Register */
-       u32     fqd_bar;        /* FQD Base Addr Register */
-       u8      res1[0x8];
-       u32     fqd_ar;         /* FQD Attributes Register */
-       u8      res2[0xc];
-       u32     pfdr_bare;      /* PFDR Extended Base Addr Register */
-       u32     pfdr_bar;       /* PFDR Base Addr Register */
-       u8      res3[0x8];
-       u32     pfdr_ar;        /* PFDR Attributes Register */
-       u8      res4[0x4c];
-       u32     qcsp_bare;      /* QCSP Extended Base Addr Register */
-       u32     qcsp_bar;       /* QCSP Base Addr Register */
-       u8      res5[0x78];
-       u32     ci_sched_cfg;   /* Initiator Scheduling Configuration */
-       u32     srcidr;         /* Source ID Register */
-       u32     liodnr;         /* LIODN Register */
-       u8      res6[4];
-       u32     ci_rlm_cfg;     /* Initiator Read Latency Monitor Cfg */
-       u32     ci_rlm_avg;     /* Initiator Read Latency Monitor Avg */
-       u8      res7[0x2e8];
-#ifdef CONFIG_SYS_FSL_QMAN_V3
-       struct {
-               u32     qcsp_lio_cfg;   /* 0x0 - SW Portal n LIO cfg */
-               u32     qcsp_io_cfg;    /* 0x4 - SW Portal n IO cfg */
-               u32     res;
-               u32     qcsp_dd_cfg;    /* 0xc - SW Portal n Dynamic Debug cfg*/
-       } qcsp[50];
-#endif
-} ccsr_qman_t;
-
-typedef struct ccsr_bman {
-       /* Not actually reserved, but irrelevant to u-boot */
-       u8      res[0xbf8];
-       u32     ip_rev_1;
-       u32     ip_rev_2;
-       u32     fbpr_bare;      /* FBPR Extended Base Addr Register */
-       u32     fbpr_bar;       /* FBPR Base Addr Register */
-       u8      res1[0x8];
-       u32     fbpr_ar;        /* FBPR Attributes Register */
-       u8      res2[0xf0];
-       u32     srcidr;         /* Source ID Register */
-       u32     liodnr;         /* LIODN Register */
-       u8      res7[0x2f4];
-} ccsr_bman_t;
-
 typedef struct ccsr_pme {
        u8      res0[0x804];
        u32     liodnbr;        /* LIODN Base Register */