u8 res24[64];
u32 pblsr; /* Preboot loader status */
u32 pamubypenr; /* PAMU bypass enable */
+#define FSL_CORENET_PAMU_BYPASS 0xffff0000
u32 dmacr1; /* DMA control */
u8 res25[4];
u32 gensr1; /* General status */
#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
#if defined(CONFIG_PPC_C29X)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
#else
#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
#endif
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_FM1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \