* Copyright 2010-2011 Freescale Semiconductor, Inc.
* Author: Dipen Dudhat <dipen.dudhat@freescale.com>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_PPC_FSL_IFC_H
#define __ASM_PPC_FSL_IFC_H
+#ifdef CONFIG_FSL_IFC
#include <config.h>
#include <common.h>
#define CSOR_NAND_PGS_512 0x00000000
#define CSOR_NAND_PGS_2K 0x00080000
#define CSOR_NAND_PGS_4K 0x00100000
+#define CSOR_NAND_PGS_8K 0x00180000
/* Spare region Size */
#define CSOR_NAND_SPRZ_MASK 0x0000E000
#define CSOR_NAND_SPRZ_SHIFT 13
#define CSOR_NAND_SPRZ_210 0x00006000
#define CSOR_NAND_SPRZ_218 0x00008000
#define CSOR_NAND_SPRZ_224 0x0000A000
+#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
/* Pages Per Block */
#define CSOR_NAND_PB_MASK 0x00000700
#define CSOR_NAND_PB_SHIFT 8
#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
+#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
+#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
+#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
+#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
#define set_ifc_ftim(i, j, v) \
(out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
-#define FSL_IFC_BANK_COUNT 4
-
enum ifc_chip_sel {
IFC_CS0,
IFC_CS1,
IFC_CS2,
IFC_CS3,
+ IFC_CS4,
+ IFC_CS5,
+ IFC_CS6,
+ IFC_CS7,
};
enum ifc_ftims {
u32 res4[0x1F3];
};
+#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
+#define IFC_CSPR_REG_LEN 148
+#define IFC_AMASK_REG_LEN 144
+#define IFC_CSOR_REG_LEN 144
+#define IFC_FTIM_REG_LEN 576
+
+#define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \
+ CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \
+ CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \
+ CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \
+ CONFIG_SYS_FSL_IFC_BANK_COUNT
+#else
+#error IFC BANK count not vaild
+#endif
+#else
+#error IFC BANK count not defined
+#endif
+
+struct fsl_ifc_cspr {
+ u32 cspr_ext;
+ u32 cspr;
+ u32 res;
+};
+
+struct fsl_ifc_amask {
+ u32 amask;
+ u32 res[0x2];
+};
+
+struct fsl_ifc_csor {
+ u32 csor;
+ u32 csor_ext;
+ u32 res;
+};
+
+struct fsl_ifc_ftim {
+ u32 ftim[4];
+ u32 res[0x8];
+};
/*
* IFC Controller Registers
*/
struct fsl_ifc {
u32 ifc_rev;
- u32 res1[0x3];
- struct {
- u32 cspr;
- u32 res2[0x2];
- } cspr_cs[FSL_IFC_BANK_COUNT];
- u32 res3[0x18];
- struct {
- u32 amask;
- u32 res4[0x2];
- } amask_cs[FSL_IFC_BANK_COUNT];
- u32 res5[0x18];
- struct {
- u32 csor;
- u32 res6[0x2];
- } csor_cs[FSL_IFC_BANK_COUNT];
- u32 res7[0x18];
- struct {
- u32 ftim[4];
- u32 res8[0x8];
- } ftim_cs[FSL_IFC_BANK_COUNT];
- u32 res9[0x60];
+ u32 res1[0x2];
+ struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
+ struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
+ struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
+ struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
u32 rb_stat;
- u32 res10[0x2];
+ u32 res6[0x2];
u32 ifc_gcr;
- u32 res11[0x2];
+ u32 res7[0x2];
u32 cm_evter_stat;
- u32 res12[0x2];
+ u32 res8[0x2];
u32 cm_evter_en;
- u32 res13[0x2];
+ u32 res9[0x2];
u32 cm_evter_intr_en;
- u32 res14[0x2];
+ u32 res10[0x2];
u32 cm_erattr0;
u32 cm_erattr1;
- u32 res15[0x2];
+ u32 res11[0x2];
u32 ifc_ccr;
u32 ifc_csr;
- u32 res16[0x2EB];
+ u32 res12[0x2EB];
struct fsl_ifc_nand ifc_nand;
struct fsl_ifc_nor ifc_nor;
struct fsl_ifc_gpcm ifc_gpcm;
};
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#undef CSPR_MSEL_NOR
+#define CSPR_MSEL_NOR CSPR_MSEL_GPCM
+#endif
+#endif /* CONFIG_FSL_IFC */
+
#endif /* __ASSEMBLY__ */
#endif /* __ASM_PPC_FSL_IFC_H */
projects / oweals / u-boot.git / blobdiff