vexpress: use correct timer address on extended memory map systems

[oweals/u-boot.git] / arch / powerpc / include / asm / fsl_ddr_sdram.h

diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index bb79335b188ec896889ceb62c738b5cc49237454..2c3c514ba30a1853c81238f846f6f8d57b28d787 100644 (file)
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -98,6 +98,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define SDRAM_CFG_SDRAM_TYPE_SHIFT     24
 #define SDRAM_CFG_DYN_PWR              0x00200000
 #define SDRAM_CFG_DBW_MASK             0x00180000
+#define SDRAM_CFG_DBW_SHIFT            19
 #define SDRAM_CFG_32_BE                        0x00080000
 #define SDRAM_CFG_16_BE                        0x00100000
 #define SDRAM_CFG_8_BE                 0x00040000
@@ -218,13 +219,13 @@ typedef struct fsl_ddr_cfg_regs_s {
 } fsl_ddr_cfg_regs_t;
 
 typedef struct memctl_options_partial_s {
-       unsigned int all_DIMMs_ECC_capable;
-       unsigned int all_DIMMs_tCKmax_ps;
-       unsigned int all_DIMMs_burst_lengths_bitmask;
-       unsigned int all_DIMMs_registered;
-       unsigned int all_DIMMs_unbuffered;
+       unsigned int all_dimms_ecc_capable;
+       unsigned int all_dimms_tckmax_ps;
+       unsigned int all_dimms_burst_lengths_bitmask;
+       unsigned int all_dimms_registered;
+       unsigned int all_dimms_unbuffered;
        /*      unsigned int lowest_common_SPD_caslat; */
-       unsigned int all_DIMMs_minimum_tRCD_ps;
+       unsigned int all_dimms_minimum_trcd_ps;
 } memctl_options_partial_t;
 
 #define DDR_DATA_BUS_WIDTH_64 0
@@ -260,10 +261,10 @@ typedef struct memctl_options_s {
        unsigned int addr_hash;
 
        /* Operational mode parameters */
-       unsigned int ECC_mode;   /* Use ECC? */
+       unsigned int ecc_mode;   /* Use ECC? */
        /* Initialize ECC using memory controller? */
-       unsigned int ECC_init_using_memctl;
-       unsigned int DQS_config;        /* Use DQS? maybe only with DDR2? */
+       unsigned int ecc_init_using_memctl;
+       unsigned int dqs_config;        /* Use DQS? maybe only with DDR2? */
        /* SREN - self-refresh during sleep */
        unsigned int self_refresh_in_sleep;
        unsigned int dynamic_power;     /* DYN_PWR */
@@ -271,11 +272,12 @@ typedef struct memctl_options_s {
        unsigned int data_bus_width;
        unsigned int burst_length;      /* BL4, OTF and BL8 */
        /* On-The-Fly Burst Chop enable */
-       unsigned int OTF_burst_chop_en;
+       unsigned int otf_burst_chop_en;
        /* mirrior DIMMs for DDR3 */
        unsigned int mirrored_dimm;
        unsigned int quad_rank_present;
        unsigned int ap_en;     /* address parity enable for RDIMM */
+       unsigned int x4_en;     /* enable x4 devices */
 
        /* Global Timing Parameters */
        unsigned int cas_latency_override;
@@ -295,11 +297,11 @@ typedef struct memctl_options_s {
        unsigned int wrlvl_ctl_3;
 
        unsigned int half_strength_driver_enable;
-       unsigned int twoT_en;
-       unsigned int threeT_en;
+       unsigned int twot_en;
+       unsigned int threet_en;
        unsigned int bstopre;
-       unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
-       unsigned int tFAW_window_four_activates_ps;     /* tFAW --  FOUR_ACT */
+       unsigned int tcke_clock_pulse_width_ps; /* tCKE */
+       unsigned int tfaw_window_four_activates_ps;     /* tFAW --  FOUR_ACT */
 
        /* Rtt impedance */
        unsigned int rtt_override;              /* rtt_override enable */
@@ -329,7 +331,30 @@ extern phys_size_t fsl_ddr_sdram(void);
 extern phys_size_t fsl_ddr_sdram_size(void);
 extern int fsl_use_spd(void);
 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-                                       unsigned int ctrl_num);
+                                       unsigned int ctrl_num, int step);
+u32 fsl_ddr_get_intl3r(void);
+
+static void __board_assert_mem_reset(void)
+{
+}
+
+static void __board_deassert_mem_reset(void)
+{
+}
+
+void board_assert_mem_reset(void)
+       __attribute__((weak, alias("__board_assert_mem_reset")));
+
+void board_deassert_mem_reset(void)
+       __attribute__((weak, alias("__board_deassert_mem_reset")));
+
+static int __board_need_mem_reset(void)
+{
+       return 0;
+}
+
+int board_need_mem_reset(void)
+       __attribute__((weak, alias("__board_need_mem_reset")));
 
 /*
  * The 85xx boards have a common prototype for fixed_sdram so put the