powerpc/t4240: Adding workaround errata A-005871

[oweals/u-boot.git] / arch / powerpc / include / asm / config_mpc85xx.h

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 965d4312c78c98e048a1d49fd468179282ba02a5..d57c178f7f23d61c2a5adcb7f2aad92900a5edfa 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -421,6 +421,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_A004580
+#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
 
 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
 #define CONFIG_SYS_PPC64               /* 64-bit core */
@@ -492,6 +493,21 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
+#elif defined(CONFIG_BSC9132)
+#define CONFIG_MAX_CPUS                        2
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB  3
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_SYS_FSL_NUM_LAWS                12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT      4
+#define CONFIG_NUM_DDR_CONTROLLERS     2
+#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
+
 #elif defined(CONFIG_PPC_T4240)
 #define CONFIG_SYS_PPC64               /* 64-bit core */
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
@@ -522,6 +538,28 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
+
+#elif defined(CONFIG_PPC_B4420)
+#define CONFIG_SYS_PPC64               /* 64-bit core */
+#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
+#define CONFIG_MAX_CPUS                        2
+#define CONFIG_SYS_FSL_NUM_CC_PLLS     4
+#define CONFIG_SYS_FSL_NUM_LAWS                32
+#define CONFIG_SYS_FSL_SEC_COMPAT      4
+#define CONFIG_SYS_NUM_FMAN            1
+#define CONFIG_SYS_NUM_FM1_DTSEC       4
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_7
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE       0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV       16
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 
 #elif defined(CONFIG_PPC_B4860)
@@ -536,7 +574,7 @@
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_NUM_FM1_DTSEC       6
 #define CONFIG_SYS_NUM_FM1_10GEC       2
-#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_NUM_DDR_CONTROLLERS     2
 #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_7
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000