powerpc: P2041: Remove macro CONFIG_PPC_P2041

[oweals/u-boot.git] / arch / powerpc / include / asm / config_mpc85xx.h

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index f16e32e97aaac94a4b5c7f72977d844822ac668f..cd47883e58e0fd071d608ad82a9f6724b2793d8a 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -85,20 +85,20 @@
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
 
-#elif defined(CONFIG_MPC8555)
+#elif defined(CONFIG_ARCH_MPC8555)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                8
 #define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 
-#elif defined(CONFIG_MPC8560)
+#elif defined(CONFIG_ARCH_MPC8560)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                8
 #define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 
-#elif defined(CONFIG_MPC8568)
+#elif defined(CONFIG_ARCH_MPC8568)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                10
 #define CONFIG_SYS_FSL_DDRC_GEN2
@@ -113,7 +113,7 @@
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 
-#elif defined(CONFIG_MPC8569)
+#elif defined(CONFIG_ARCH_MPC8569)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                10
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
@@ -129,7 +129,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
-#elif defined(CONFIG_MPC8572)
+#elif defined(CONFIG_ARCH_MPC8572)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -140,7 +140,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
-#elif defined(CONFIG_P1010)
+#elif defined(CONFIG_ARCH_P1010)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS                12
@@ -169,7 +169,7 @@
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
 /* P1011 is single core version of P1020 */
-#elif defined(CONFIG_P1011)
+#elif defined(CONFIG_ARCH_P1011)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -183,74 +183,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
-/* P1012 is single core version of P1021 */
-#elif defined(CONFIG_P1012)
-#define CONFIG_MAX_CPUS                        1
-#define CONFIG_SYS_FSL_NUM_LAWS                12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        2
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
-#define CONFIG_TSECV2
-#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT      2
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define QE_MURAM_SIZE                  0x6000UL
-#define MAX_QE_RISC                    1
-#define QE_NUM_OF_SNUM                 28
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-/* P1013 is single core version of P1022 */
-#elif defined(CONFIG_P1013)
-#define CONFIG_MAX_CPUS                        1
-#define CONFIG_SYS_FSL_NUM_LAWS                12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
-#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT      2
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_FSL_SATA_ERRATUM_A001
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_P1014)
-#define CONFIG_MAX_CPUS                        1
-#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS                12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB  3
-#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT      4
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_NUM_DDR_CONTROLLERS     1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
-#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-
-/* P1017 is single core version of P1023 */
-#elif defined(CONFIG_P1017)
-#define CONFIG_MAX_CPUS                        1
-#define CONFIG_SYS_FSL_NUM_LAWS                12
-#define CONFIG_SYS_FSL_SEC_COMPAT      4
-#define CONFIG_SYS_NUM_FMAN            1
-#define CONFIG_SYS_NUM_FM1_DTSEC       2
-#define CONFIG_NUM_DDR_CONTROLLERS     1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
-#define CONFIG_SYS_QMAN_NUM_PORTALS    3
-#define CONFIG_SYS_BMAN_NUM_PORTALS    3
-#define CONFIG_SYS_FM_MURAM_SIZE       0x10000
-#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff600000
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_P1020)
+#elif defined(CONFIG_ARCH_P1020)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -266,7 +199,7 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
 #endif
 
-#elif defined(CONFIG_P1021)
+#elif defined(CONFIG_ARCH_P1021)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -283,7 +216,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
 
-#elif defined(CONFIG_P1022)
+#elif defined(CONFIG_ARCH_P1022)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -298,7 +231,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_A004477
 
-#elif defined(CONFIG_P1023)
+#elif defined(CONFIG_ARCH_P1023)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
@@ -317,7 +250,7 @@
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
 
 /* P1024 is lower end variant of P1020 */
-#elif defined(CONFIG_P1024)
+#elif defined(CONFIG_ARCH_P1024)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -332,7 +265,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 /* P1025 is lower end variant of P1021 */
-#elif defined(CONFIG_P1025)
+#elif defined(CONFIG_ARCH_P1025)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
@@ -349,20 +282,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
-/* P2010 is single core version of P2020 */
-#elif defined(CONFIG_P2010)
-#define CONFIG_MAX_CPUS                        1
-#define CONFIG_SYS_FSL_NUM_LAWS                12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
-#define CONFIG_SYS_FSL_SEC_COMPAT      2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_P2020)
+#elif defined(CONFIG_ARCH_P2020)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -380,7 +300,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004477
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
 
-#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
+#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_MAX_CPUS                        4