powerpc: P2041: Remove macro CONFIG_PPC_P2041

[oweals/u-boot.git] / arch / powerpc / include / asm / config_mpc85xx.h

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 69e05923f68c4e55db2d2c4429d33b44d1503e28..cd47883e58e0fd071d608ad82a9f6724b2793d8a 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -35,7 +35,7 @@
 #define CONFIG_SYS_NUM_TLBCAMS         16
 #endif
 
-#if defined(CONFIG_MPC8536)
+#if defined(CONFIG_ARCH_MPC8536)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  1
@@ -44,20 +44,20 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
-#elif defined(CONFIG_MPC8540)
+#elif defined(CONFIG_ARCH_MPC8540)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                8
 #define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 
-#elif defined(CONFIG_MPC8541)
+#elif defined(CONFIG_ARCH_MPC8541)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                8
 #define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 
-#elif defined(CONFIG_MPC8544)
+#elif defined(CONFIG_ARCH_MPC8544)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                10
 #define CONFIG_SYS_FSL_DDRC_GEN2
@@ -66,7 +66,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
-#elif defined(CONFIG_MPC8548)
+#elif defined(CONFIG_ARCH_MPC8548)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                10
 #define CONFIG_SYS_FSL_DDRC_GEN2
@@ -85,20 +85,20 @@
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
 
-#elif defined(CONFIG_MPC8555)
+#elif defined(CONFIG_ARCH_MPC8555)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                8
 #define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 
-#elif defined(CONFIG_MPC8560)
+#elif defined(CONFIG_ARCH_MPC8560)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                8
 #define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 
-#elif defined(CONFIG_MPC8568)
+#elif defined(CONFIG_ARCH_MPC8568)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                10
 #define CONFIG_SYS_FSL_DDRC_GEN2
@@ -113,7 +113,7 @@
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 
-#elif defined(CONFIG_MPC8569)
+#elif defined(CONFIG_ARCH_MPC8569)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                10
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
@@ -129,7 +129,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
-#elif defined(CONFIG_MPC8572)
+#elif defined(CONFIG_ARCH_MPC8572)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -140,7 +140,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
-#elif defined(CONFIG_P1010)
+#elif defined(CONFIG_ARCH_P1010)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS                12
@@ -162,12 +162,14 @@
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A007075
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_A006261
+#define CONFIG_SYS_FSL_ERRATUM_A004477
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
 /* P1011 is single core version of P1020 */
-#elif defined(CONFIG_P1011)
+#elif defined(CONFIG_ARCH_P1011)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -181,74 +183,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
-/* P1012 is single core version of P1021 */
-#elif defined(CONFIG_P1012)
-#define CONFIG_MAX_CPUS                        1
-#define CONFIG_SYS_FSL_NUM_LAWS                12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        2
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
-#define CONFIG_TSECV2
-#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT      2
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define QE_MURAM_SIZE                  0x6000UL
-#define MAX_QE_RISC                    1
-#define QE_NUM_OF_SNUM                 28
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-/* P1013 is single core version of P1022 */
-#elif defined(CONFIG_P1013)
-#define CONFIG_MAX_CPUS                        1
-#define CONFIG_SYS_FSL_NUM_LAWS                12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
-#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT      2
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_FSL_SATA_ERRATUM_A001
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_P1014)
-#define CONFIG_MAX_CPUS                        1
-#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS                12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB  3
-#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT      4
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_NUM_DDR_CONTROLLERS     1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
-#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-
-/* P1017 is single core version of P1023 */
-#elif defined(CONFIG_P1017)
-#define CONFIG_MAX_CPUS                        1
-#define CONFIG_SYS_FSL_NUM_LAWS                12
-#define CONFIG_SYS_FSL_SEC_COMPAT      4
-#define CONFIG_SYS_NUM_FMAN            1
-#define CONFIG_SYS_NUM_FM1_DTSEC       2
-#define CONFIG_NUM_DDR_CONTROLLERS     1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
-#define CONFIG_SYS_QMAN_NUM_PORTALS    3
-#define CONFIG_SYS_BMAN_NUM_PORTALS    3
-#define CONFIG_SYS_FM_MURAM_SIZE       0x10000
-#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff600000
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_P1020)
+#elif defined(CONFIG_ARCH_P1020)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -264,7 +199,7 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
 #endif
 
-#elif defined(CONFIG_P1021)
+#elif defined(CONFIG_ARCH_P1021)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -281,7 +216,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
 
-#elif defined(CONFIG_P1022)
+#elif defined(CONFIG_ARCH_P1022)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -294,8 +229,9 @@
 #define CONFIG_FSL_SATA_ERRATUM_A001
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
 
-#elif defined(CONFIG_P1023)
+#elif defined(CONFIG_ARCH_P1023)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
@@ -314,7 +250,7 @@
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
 
 /* P1024 is lower end variant of P1020 */
-#elif defined(CONFIG_P1024)
+#elif defined(CONFIG_ARCH_P1024)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -329,10 +265,10 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 /* P1025 is lower end variant of P1021 */
-#elif defined(CONFIG_P1025)
+#elif defined(CONFIG_ARCH_P1025)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -346,20 +282,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
-/* P2010 is single core version of P2020 */
-#elif defined(CONFIG_P2010)
-#define CONFIG_MAX_CPUS                        1
-#define CONFIG_SYS_FSL_NUM_LAWS                12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
-#define CONFIG_SYS_FSL_SEC_COMPAT      2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_P2020)
+#elif defined(CONFIG_ARCH_P2020)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
@@ -374,9 +297,10 @@
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
 
-#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
+#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_MAX_CPUS                        4
@@ -575,7 +499,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 
-#elif defined(CONFIG_BSC9131)
+#elif defined(CONFIG_ARCH_BSC9131)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS                12
@@ -591,9 +515,10 @@
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
-#elif defined(CONFIG_BSC9132)
+#elif defined(CONFIG_ARCH_BSC9132)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  3
 #define CONFIG_FSL_SDHC_V2_3
@@ -615,6 +540,7 @@
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_A005434
+#define CONFIG_SYS_FSL_ERRATUM_A004477
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
 #define CONFIG_ESDHC_HC_BLK_ADDR
@@ -635,6 +561,7 @@
 #define CONFIG_SYS_NUM_FM2_DTSEC       8
 #define CONFIG_SYS_NUM_FM2_10GEC       2
 #define CONFIG_NUM_DDR_CONTROLLERS     3
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #else
 #define CONFIG_SYS_NUM_FM1_DTSEC       6
 #define CONFIG_SYS_NUM_FM1_10GEC       1
@@ -676,7 +603,6 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
-#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006593
@@ -723,6 +649,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A006475
 #define CONFIG_SYS_FSL_ERRATUM_A006384
 #define CONFIG_SYS_FSL_ERRATUM_A007212
+#define CONFIG_SYS_FSL_ERRATUM_A004477
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
@@ -769,7 +696,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
-#define CONFIG_SYS_SDHC_CLOCK          0
 #define CONFIG_SYS_FSL_NUM_LAWS                16
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SEC_COMPAT      5
@@ -785,19 +711,24 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_FM_PLAT_CLK_DIV 1
 #define CONFIG_SYS_FM1_CLK             CONFIG_FM_PLAT_CLK_DIV
+#define CONFIG_SYS_SDHC_CLK            0/* Select SDHC CLK begining from PLL1
+                                           per rcw field value */
+#define CONFIG_SYS_SDHC_CLK_2_PLL      /* Select SDHC CLK from 2 PLLs */
 #define CONFIG_SYS_FM_MURAM_SIZE       0x30000
 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE                  0x6000UL
 #define MAX_QE_RISC                    1
 #define QE_NUM_OF_SNUM                 28
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+#define CONFIG_SYS_FSL_ERRATUM_A008378
+#define CONFIG_SYS_FSL_ERRATUM_A009663
 
 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
@@ -817,7 +748,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLL      2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
-#define CONFIG_SYS_SDHC_CLOCK          0
 #define CONFIG_SYS_FSL_NUM_LAWS                16
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SEC_COMPAT      5
@@ -830,6 +760,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_DDR_VER  FSL_DDR_VER_5_0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_FM1_CLK             0
+#define CONFIG_SYS_SDHC_CLK            0/* Select SDHC CLK begining from PLL1
+                                           per rcw field value */
 #define CONFIG_QBMAN_CLK_DIV           1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x30000
 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
@@ -844,6 +776,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define MAX_QE_RISC                    1
 #define QE_NUM_OF_SNUM                 28
 #define CONFIG_SYS_FSL_SFP_VER_3_0
+#define CONFIG_SYS_FSL_ERRATUM_A008378
+#define CONFIG_SYS_FSL_ERRATUM_A009663
 
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define CONFIG_E6500
@@ -877,6 +811,9 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_PME_PLAT_CLK_DIV                1
 #define CONFIG_SYS_PME_CLK             CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FM1_CLK             0
+#define CONFIG_SYS_SDHC_CLK            1/* Select SDHC CLK begining from PLL2
+                                           per rcw field value */
+#define CONFIG_SYS_SDHC_CLK_2_PLL      /* Select SDHC CLK from 2 PLLs */
 #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_FMAN_V3
@@ -890,7 +827,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_ISBC_VER                2
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006379
@@ -898,7 +834,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
 
-#elif defined(CONFIG_PPC_C29X)
+#elif defined(CONFIG_ARCH_C29X)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS                12
@@ -911,6 +847,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  3
+#define CONFIG_SYS_FSL_SEC_IDX_OFFSET  0x20000
 
 #elif defined(CONFIG_QEMU_E500)
 #define CONFIG_MAX_CPUS                        1
@@ -937,4 +875,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_DDRC_GEN3
 #endif
 
+#if !defined(CONFIG_ARCH_C29X)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
+#endif
+
 #endif /* _ASM_MPC85xx_CONFIG_H_ */