gpio: mpc8xxx: Rename Kconfig option, structures, and functions

[oweals/u-boot.git] / arch / powerpc / include / asm / config_mpc85xx.h

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 92c96d7e1293b089eec78c4136200039c6a4d7cc..6fd218a428120817c932c48742bea41dee2e339f 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -117,7 +117,6 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
 
 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_NUM_FMAN            1
@@ -136,7 +135,6 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_P3041)
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_NUM_FMAN            1
@@ -155,7 +153,6 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     4
 #define CONFIG_SYS_NUM_FMAN            2
@@ -175,8 +172,6 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
 
 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
-#define CONFIG_SYS_PPC64               /* 64-bit core */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_NUM_FMAN            1
@@ -195,8 +190,6 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
 
 #elif defined(CONFIG_ARCH_P5040)
-#define CONFIG_SYS_PPC64
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     3
 #define CONFIG_SYS_NUM_FMAN            2
@@ -238,9 +231,7 @@
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
-#define CONFIG_SYS_PPC64               /* 64-bit core */
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #ifdef CONFIG_ARCH_T4240
@@ -283,9 +274,7 @@
 #define CONFIG_SYS_FSL_PCI_VER_3_X
 
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
-#define CONFIG_SYS_PPC64               /* 64-bit core */
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #define CONFIG_HETROGENOUS_CLUSTERS     /* DSP/SC3900 core clusters */
 #define CONFIG_PPC_CLUSTER_START       0 /*Start index of ppc clusters*/
@@ -334,7 +323,6 @@
 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
 #define CONFIG_E5500
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
@@ -367,7 +355,6 @@
 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
 #define CONFIG_E5500
 #define CONFIG_FSL_CORENET          /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3  /* QMAN version 3 */
 #define CONFIG_SYS_FMAN_V3
@@ -397,9 +384,7 @@
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
-#define CONFIG_SYS_PPC64               /* 64-bit core */
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_FSL_QMAN_V3