-/*-----------------------------------------------------------------------------+
- * This source code is dual-licensed. You may use it under the terms of
- * the GNU General Public license version 2, or under the license below.
- *
- * This source code has been made available to you by IBM on an AS-IS
- * basis. Anyone receiving this source is licensed under IBM
- * copyrights to use it in any way he or she deems fit, including
- * copying it, modifying it, compiling it, and redistributing it either
- * with or without modifications. No license under IBM patents or
- * patent applications is to be implied by the copyright license.
- *
- * Any user of this software should understand that IBM cannot provide
- * technical support for this software and will not be responsible for
- * any consequences resulting from the use of this software.
- *
- * Any person who transfers this source code or any derivative work
- * must include the IBM copyright notice, this paragraph, and the
- * preceding two paragraphs in the transferred software.
- *
- * COPYRIGHT I B M CORPORATION 1995
- * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
- *-----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
+/*
+ * SPDX-License-Identifier: GPL-2.0 IBM-pibs
*
* File Name: 405gp_pci.c
*
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
-#if defined(CONFIG_PMC405)
-ushort pmc405_pci_subsys_deviceid(void);
-#endif
-
/*#define DEBUG*/
/*
#endif
unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
-#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
+#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
+ || defined(CONFIG_TARGET_MIP405T)
unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
ptmla_str = getenv("ptm1la");
ptmms_str = getenv("ptm1ms");
if(NULL != ptmla_str && NULL != ptmms_str ) {
- ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
+ ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
}
ptmla_str = getenv("ptm2la");
ptmms_str = getenv("ptm2ms");
if(NULL != ptmla_str && NULL != ptmms_str ) {
- ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
+ ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
}
#endif
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
}
-#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
+#if !(defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
+ || defined(CONFIG_TARGET_MIP405T))
/*
*As is these functs get called out of flash Not a horrible
*-----------------------------------------------------------------------------*/
#if defined(CONFIG_440)
+#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
static struct pci_controller ppc440_hose = {0};
+#endif
/*
* This routine is called to determine if a pci scan should be
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
- mfsdr(SD0_AMP1, reg);
- mtsdr(SD0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
- reg = mfdcr(PLB3_ACR);
- mtdcr(PLB3_ACR, reg | 0x80000000);
+ mfsdr(SDR0_AMP1, reg);
+ mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
+ reg = mfdcr(PLB3A0_ACR);
+ mtdcr(PLB3A0_ACR, reg | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
- mfsdr(SD0_AMP0, reg);
- mtsdr(SD0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
- reg = mfdcr(PLB4_ACR) | 0xa0000000;
- mtdcr(PLB4_ACR, reg);
+ mfsdr(SDR0_AMP0, reg);
+ mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
+ reg = mfdcr(PLB4A0_ACR) | 0xa0000000;
+ mtdcr(PLB4A0_ACR, reg);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
- reg = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
- reg = (reg & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
- reg = (reg & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
- reg = (reg & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
- mtdcr(PLB0_ACR, reg);
+ reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
+ reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
+ reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
+ reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
+ mtdcr(PLB4A0_ACR, reg);
/* Segment1 */
- reg = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
- reg = (reg & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
- reg = (reg & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
- reg = (reg & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
- mtdcr(PLB1_ACR, reg);
+ reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
+ reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
+ reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
+ reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
+ mtdcr(PLB4A1_ACR, reg);
#if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
hose->fixup_irq = board_pci_fixup_irq;
__attribute__((weak, alias("__pci_master_init")));
#endif /* CONFIG_SYS_PCI_MASTER_INIT */
-int pci_440_init (struct pci_controller *hose)
+#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
+static int pci_440_init (struct pci_controller *hose)
{
int reg_num = 0;
}
return hose->last_busno;
}
+#endif
void pci_init_board(void)
{
- int busno;
+ int busno = 0;
- busno = pci_440_init (&ppc440_hose);
+ /*
+ * Only init PCI when either master or target functionality
+ * is selected.
+ */
+#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
+ busno = pci_440_init(&ppc440_hose);
+ if (busno < 0)
+ return;
+#endif
#if (defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
!defined(CONFIG_PCI_DISABLE_PCIE)